6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-11-06 20:18:14 +00:00
Code Issues Projects Releases Wiki Activity

Generate better select code by allowing the target to use scalar select, and not sign-extend.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163086 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nadav Rotem
2012-09-02 08:20:07 +00:00
parent d906017c1a
commit f55ef64544
2 changed files with 5 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
View File

@@ -475,10 +475,9 @@ SDValue VectorLegalizer::ExpandSELECT(SDValue Op) {
// What is the size of each element in the vector mask. // What is the size of each element in the vector mask.
EVT BitTy = MaskTy.getScalarType(); EVT BitTy = MaskTy.getScalarType();
// Turn the mask into an all-one or all-zero word. Mask = DAG.getNode(ISD::SELECT, DL, BitTy, Mask,
Mask = DAG.getAnyExtOrTrunc(Mask, DL, BitTy); DAG.getConstant(APInt::getAllOnesValue(BitTy.getSizeInBits()), BitTy),
Mask = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, BitTy, Mask, DAG.getConstant(3, BitTy));
DAG.getValueType(MVT::i1));
// Broadcast the mask so that the entire vector is all-one or all zero. // Broadcast the mask so that the entire vector is all-one or all zero.
SmallVector<SDValue, 8> Ops(NumElem, Mask); SmallVector<SDValue, 8> Ops(NumElem, Mask);

2
test/CodeGen/ARM/2012-08-30-select.ll
View File

@@ -2,6 +2,8 @@
; rdar://12201387 ; rdar://12201387
;CHECK: select_s_v_v ;CHECK: select_s_v_v
;CHECK: it eq
;CHECK-NEXT: moveq.w r2, #-1
;CHECK: vbsl ;CHECK: vbsl
;CHECK: bx ;CHECK: bx
define <16 x i8> @select_s_v_v(i32 %avail, i8* %bar) { define <16 x i8> @select_s_v_v(i32 %avail, i8* %bar) {