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Provide correct NEON encodings for vdup.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117475 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson
2010-10-27 19:25:54 +00:00
parent 6dad10ed66
commit f587a9352a
3 changed files with 157 additions and 8 deletions
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18
lib/Target/ARM/ARMInstrFormats.td
View File

@@ -1867,6 +1867,15 @@ class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
let Pattern = pattern;
list<Predicate> Predicates = [HasNEON];
bits<5> Vd;
bits<4> Rt;
bits<4> p;
let Inst{31-28} = p{3-0};
let Inst{7} = Vd{4};
let Inst{19-16} = Vd{3-0};
let Inst{15-12} = Rt{3-0};
}
class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
dag oops, dag iops, InstrItinClass itin,
@@ -1895,6 +1904,15 @@ class NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops,
let Inst{11-7} = 0b11000;
let Inst{6} = op6;
let Inst{4} = 0;
bits<5> Vd;
bits<5> Vm;
bits<4> lane;
let Inst{22} = Vd{4};
let Inst{15-12} = Vd{3-0};
let Inst{5} = Vm{4};
let Inst{3-0} = Vm{3-0};
}
// NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON

32
lib/Target/ARM/ARMInstrNEON.td
View File

@@ -3679,14 +3679,30 @@ class VDUPLNQ<bits<4> op19_16, string OpcodeStr, string Dt,
// Inst{19-16} is partially specified depending on the element size.
def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8>;
def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16>;
def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32>;
def VDUPLNfd : VDUPLND<{?,1,0,0}, "vdup", "32", v2f32>;
def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8>;
def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16>;
def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32>;
def VDUPLNfq : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4f32, v2f32>;
def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8> {
let Inst{19-17} = lane{2-0};
}
def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16> {
let Inst{19-18} = lane{1-0};
}
def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32> {
let Inst{19} = lane{0};
}
def VDUPLNfd : VDUPLND<{?,1,0,0}, "vdup", "32", v2f32> {
let Inst{19} = lane{0};
}
def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8> {
let Inst{19-17} = lane{2-0};
}
def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16> {
let Inst{19-18} = lane{1-0};
}
def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32> {
let Inst{19} = lane{0};
}
def VDUPLNfq : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4f32, v2f32> {
let Inst{19} = lane{0};
}
def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
(v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,