6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-10-25 10:27:04 +00:00
Code Issues Projects Releases Wiki Activity

[mips] Fix definitions of multiply, multiply-add/sub and divide instructions.

Browse Source 
The new instructions have explicit register output operands and use table-gen
patterns instead of C++ code to do instruction selection.

Mips16's instructions are unaffected by this change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178403 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
2013-03-30 01:36:35 +00:00
parent 9cf0724cc3
commit f5926fd844
7 changed files with 199 additions and 70 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
lib/Target/Mips/MipsSEISelDAGToDAG.cpp
View File

@@ -450,6 +450,19 @@ std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
ReplaceUses(SDValue(Node, 0), ResNode);
return std::make_pair(true, ResNode.getNode());
}
case MipsISD::InsertLOHI: {
unsigned RCID = Subtarget.hasDSP() ? Mips::ACRegsDSPRegClassID :
Mips::ACRegsRegClassID;
SDValue RegClass = CurDAG->getTargetConstant(RCID, MVT::i32);
SDValue LoIdx = CurDAG->getTargetConstant(Mips::sub_lo, MVT::i32);
SDValue HiIdx = CurDAG->getTargetConstant(Mips::sub_hi, MVT::i32);
const SDValue Ops[] = { RegClass, Node->getOperand(0), LoIdx,
Node->getOperand(1), HiIdx };
SDNode *Res = CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL,
MVT::Untyped, Ops, 5);
return std::make_pair(true, Res);
}
}
return std::make_pair(false, (SDNode*)NULL);