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https://github.com/c64scene-ar/llvm-6502.git
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Add PPC FP rounding instructions fri[mnpz]
These instructions are available on the P5x (and later) and on the A2. They implement the standard floating-point rounding operations (floor, trunc, etc.). One caveat: frin (round to nearest) does not implement "ties to even", and so is only enabled in fast-math mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178337 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel
parent
ef484a376c
commit
f5d5c43460
@ -59,6 +59,8 @@ def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true",
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"Enable the fsqrt instruction">;
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def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
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"Enable the stfiwx instruction">;
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def FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true",
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"Enable the fri[mnpz] instructions">;
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def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true",
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"Enable the isel instruction">;
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def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD", "true",
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@ -76,7 +78,6 @@ def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true",
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// CMPB p6, p6x, p7 cmpb
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// DFP p6, p6x, p7 decimal floating-point instructions
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// FLT_CVT p7 fcfids, fcfidu, fcfidus, fcfiduz, fctiwuz
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// FPRND p5x, p6, p6x, p7 frim, frin, frip, friz
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// FRE p5 through p7 fre (vs. fres, available since p3)
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// FRSQRTES p5 through p7 frsqrtes (vs. frsqrte, available since p3)
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// LFIWAX p6, p6x, p7 lfiwax
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@ -132,14 +133,14 @@ def : ProcessorModel<"e5500", PPCE5500Model,
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FeatureSTFIWX, FeatureBookE, FeatureISEL]>;
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def : Processor<"a2", PPCA2Itineraries,
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[DirectiveA2, FeatureBookE, FeatureMFOCRF,
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FeatureFSqrt, FeatureSTFIWX, FeatureISEL,
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FeaturePOPCNTD, FeatureLDBRX, Feature64Bit
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/*, Feature64BitRegs */]>;
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FeatureFSqrt, FeatureSTFIWX, FeatureFPRND,
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FeatureISEL, FeaturePOPCNTD, FeatureLDBRX,
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Feature64Bit /*, Feature64BitRegs */]>;
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def : Processor<"a2q", PPCA2Itineraries,
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[DirectiveA2, FeatureBookE, FeatureMFOCRF,
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FeatureFSqrt, FeatureSTFIWX, FeatureISEL,
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FeaturePOPCNTD, FeatureLDBRX, Feature64Bit
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/*, Feature64BitRegs */, FeatureQPX]>;
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FeatureFSqrt, FeatureSTFIWX, FeatureFPRND,
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FeatureISEL, FeaturePOPCNTD, FeatureLDBRX,
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Feature64Bit /*, Feature64BitRegs */, FeatureQPX]>;
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def : Processor<"pwr3", G5Itineraries,
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[DirectivePwr3, FeatureAltivec, FeatureMFOCRF,
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FeatureSTFIWX, Feature64Bit]>;
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@ -151,19 +152,21 @@ def : Processor<"pwr5", G5Itineraries,
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FeatureFSqrt, FeatureSTFIWX, Feature64Bit]>;
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def : Processor<"pwr5x", G5Itineraries,
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[DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
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FeatureFSqrt, FeatureSTFIWX, Feature64Bit]>;
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FeatureFSqrt, FeatureSTFIWX, FeatureFPRND,
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Feature64Bit]>;
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def : Processor<"pwr6", G5Itineraries,
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[DirectivePwr6, FeatureAltivec,
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FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
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Feature64Bit /*, Feature64BitRegs */]>;
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FeatureFPRND, Feature64Bit /*, Feature64BitRegs */]>;
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def : Processor<"pwr6x", G5Itineraries,
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[DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
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FeatureFSqrt, FeatureSTFIWX, Feature64Bit]>;
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FeatureFSqrt, FeatureSTFIWX, FeatureFPRND,
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Feature64Bit]>;
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def : Processor<"pwr7", G5Itineraries,
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[DirectivePwr7, FeatureAltivec,
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FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
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FeatureISEL, FeaturePOPCNTD, FeatureLDBRX,
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Feature64Bit /*, Feature64BitRegs */]>;
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FeatureFPRND, FeatureISEL, FeaturePOPCNTD,
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FeatureLDBRX, Feature64Bit /*, Feature64BitRegs */]>;
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def : Processor<"ppc", G3Itineraries, [Directive32]>;
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def : Processor<"ppc64", G5Itineraries,
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[Directive64, FeatureAltivec,
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@ -158,6 +158,23 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
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setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
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setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
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if (Subtarget->hasFPRND()) {
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setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
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setOperationAction(ISD::FCEIL, MVT::f64, Legal);
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setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
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setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
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setOperationAction(ISD::FCEIL, MVT::f32, Legal);
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setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
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// frin does not implement "ties to even." Thus, this is safe only in
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// fast-math mode.
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if (TM.Options.UnsafeFPMath) {
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setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
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setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
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}
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}
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// PowerPC does not have BSWAP, CTPOP or CTTZ
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setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
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setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
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@ -1128,9 +1128,38 @@ let Uses = [RM] in {
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def FCTIWZ : XForm_26<63, 15, (outs F8RC:$frD), (ins F8RC:$frB),
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"fctiwz $frD, $frB", FPGeneral,
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[(set f64:$frD, (PPCfctiwz f64:$frB))]>;
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def FRSP : XForm_26<63, 12, (outs F4RC:$frD), (ins F8RC:$frB),
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"frsp $frD, $frB", FPGeneral,
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[(set f32:$frD, (fround f64:$frB))]>;
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// The frin -> nearbyint mapping is valid only in fast-math mode.
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def FRIND : XForm_26<63, 392, (outs F8RC:$frD), (ins F8RC:$frB),
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"frin $frD, $frB", FPGeneral,
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[(set f64:$frD, (fnearbyint f64:$frB))]>;
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def FRINS : XForm_26<63, 392, (outs F4RC:$frD), (ins F4RC:$frB),
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"frin $frD, $frB", FPGeneral,
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[(set f32:$frD, (fnearbyint f32:$frB))]>;
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def FRIPD : XForm_26<63, 456, (outs F8RC:$frD), (ins F8RC:$frB),
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"frip $frD, $frB", FPGeneral,
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[(set f64:$frD, (fceil f64:$frB))]>;
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def FRIPS : XForm_26<63, 456, (outs F4RC:$frD), (ins F4RC:$frB),
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"frip $frD, $frB", FPGeneral,
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[(set f32:$frD, (fceil f32:$frB))]>;
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def FRIZD : XForm_26<63, 424, (outs F8RC:$frD), (ins F8RC:$frB),
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"friz $frD, $frB", FPGeneral,
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[(set f64:$frD, (ftrunc f64:$frB))]>;
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def FRIZS : XForm_26<63, 424, (outs F4RC:$frD), (ins F4RC:$frB),
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"friz $frD, $frB", FPGeneral,
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[(set f32:$frD, (ftrunc f32:$frB))]>;
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def FRIMD : XForm_26<63, 488, (outs F8RC:$frD), (ins F8RC:$frB),
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"frim $frD, $frB", FPGeneral,
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[(set f64:$frD, (ffloor f64:$frB))]>;
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def FRIMS : XForm_26<63, 488, (outs F4RC:$frD), (ins F4RC:$frB),
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"frim $frD, $frB", FPGeneral,
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[(set f32:$frD, (ffloor f32:$frB))]>;
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def FSQRT : XForm_26<63, 22, (outs F8RC:$frD), (ins F8RC:$frB),
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"fsqrt $frD, $frB", FPSqrt,
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[(set f64:$frD, (fsqrt f64:$frB))]>;
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@ -39,6 +39,7 @@ PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU,
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, HasQPX(false)
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, HasFSQRT(false)
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, HasSTFIWX(false)
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, HasFPRND(false)
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, HasISEL(false)
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, HasPOPCNTD(false)
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, HasLDBRX(false)
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@ -78,6 +78,7 @@ protected:
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bool HasQPX;
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bool HasFSQRT;
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bool HasSTFIWX;
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bool HasFPRND;
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bool HasISEL;
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bool HasPOPCNTD;
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bool HasLDBRX;
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@ -157,6 +158,7 @@ public:
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// Specific obvious features.
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bool hasFSQRT() const { return HasFSQRT; }
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bool hasSTFIWX() const { return HasSTFIWX; }
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bool hasFPRND() const { return HasFPRND; }
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bool hasAltivec() const { return HasAltivec; }
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bool hasQPX() const { return HasQPX; }
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bool hasMFOCRF() const { return HasMFOCRF; }
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108
test/CodeGen/PowerPC/rounding-ops.ll
Normal file
108
test/CodeGen/PowerPC/rounding-ops.ll
Normal file
@ -0,0 +1,108 @@
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; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s
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; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -enable-unsafe-fp-math | FileCheck -check-prefix=CHECK-FM %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define float @test1(float %x) nounwind {
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%call = tail call float @floorf(float %x) nounwind readnone
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ret float %call
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; CHECK: test1:
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; CHECK: frim 1, 1
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; CHECK-FM: test1:
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; CHECK-FM: frim 1, 1
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}
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declare float @floorf(float) nounwind readnone
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define double @test2(double %x) nounwind {
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%call = tail call double @floor(double %x) nounwind readnone
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ret double %call
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; CHECK: test2:
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; CHECK: frim 1, 1
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; CHECK-FM: test2:
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; CHECK-FM: frim 1, 1
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}
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declare double @floor(double) nounwind readnone
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define float @test3(float %x) nounwind {
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%call = tail call float @nearbyintf(float %x) nounwind readnone
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ret float %call
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; CHECK: test3:
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; CHECK-NOT: frin
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; CHECK-FM: test3:
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; CHECK-FM: frin 1, 1
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}
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declare float @nearbyintf(float) nounwind readnone
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define double @test4(double %x) nounwind {
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%call = tail call double @nearbyint(double %x) nounwind readnone
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ret double %call
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; CHECK: test4:
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; CHECK-NOT: frin
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; CHECK-FM: test4:
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; CHECK-FM: frin 1, 1
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}
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declare double @nearbyint(double) nounwind readnone
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define float @test5(float %x) nounwind {
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%call = tail call float @ceilf(float %x) nounwind readnone
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ret float %call
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; CHECK: test5:
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; CHECK: frip 1, 1
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; CHECK-FM: test5:
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; CHECK-FM: frip 1, 1
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}
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declare float @ceilf(float) nounwind readnone
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define double @test6(double %x) nounwind {
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%call = tail call double @ceil(double %x) nounwind readnone
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ret double %call
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; CHECK: test6:
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; CHECK: frip 1, 1
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; CHECK-FM: test6:
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; CHECK-FM: frip 1, 1
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}
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declare double @ceil(double) nounwind readnone
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define float @test9(float %x) nounwind {
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%call = tail call float @truncf(float %x) nounwind readnone
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ret float %call
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; CHECK: test9:
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; CHECK: friz 1, 1
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; CHECK-FM: test9:
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; CHECK-FM: friz 1, 1
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}
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declare float @truncf(float) nounwind readnone
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define double @test10(double %x) nounwind {
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%call = tail call double @trunc(double %x) nounwind readnone
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ret double %call
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; CHECK: test10:
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; CHECK: friz 1, 1
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; CHECK-FM: test10:
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; CHECK-FM: friz 1, 1
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}
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declare double @trunc(double) nounwind readnone
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@ -13,8 +13,8 @@ define <2 x double> @floor_v2f64(<2 x double> %p)
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ret <2 x double> %t
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}
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; CHECK: floor_v2f64:
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; CHECK: bl floor
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; CHECK: bl floor
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; CHECK: frim
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; CHECK: frim
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declare <4 x double> @llvm.floor.v4f64(<4 x double> %p)
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define <4 x double> @floor_v4f64(<4 x double> %p)
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@ -23,10 +23,10 @@ define <4 x double> @floor_v4f64(<4 x double> %p)
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ret <4 x double> %t
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}
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; CHECK: floor_v4f64:
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; CHECK: bl floor
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; CHECK: bl floor
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; CHECK: bl floor
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; CHECK: bl floor
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; CHECK: frim
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; CHECK: frim
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; CHECK: frim
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; CHECK: frim
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declare <2 x double> @llvm.ceil.v2f64(<2 x double> %p)
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define <2 x double> @ceil_v2f64(<2 x double> %p)
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@ -35,8 +35,8 @@ define <2 x double> @ceil_v2f64(<2 x double> %p)
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ret <2 x double> %t
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}
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; CHECK: ceil_v2f64:
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; CHECK: bl ceil
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; CHECK: bl ceil
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; CHECK: frip
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; CHECK: frip
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declare <4 x double> @llvm.ceil.v4f64(<4 x double> %p)
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define <4 x double> @ceil_v4f64(<4 x double> %p)
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@ -45,10 +45,10 @@ define <4 x double> @ceil_v4f64(<4 x double> %p)
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ret <4 x double> %t
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}
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; CHECK: ceil_v4f64:
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; CHECK: bl ceil
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; CHECK: bl ceil
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; CHECK: bl ceil
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; CHECK: bl ceil
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; CHECK: frip
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; CHECK: frip
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; CHECK: frip
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; CHECK: frip
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declare <2 x double> @llvm.trunc.v2f64(<2 x double> %p)
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define <2 x double> @trunc_v2f64(<2 x double> %p)
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@ -57,8 +57,8 @@ define <2 x double> @trunc_v2f64(<2 x double> %p)
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ret <2 x double> %t
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}
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; CHECK: trunc_v2f64:
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; CHECK: bl trunc
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; CHECK: bl trunc
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; CHECK: friz
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; CHECK: friz
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declare <4 x double> @llvm.trunc.v4f64(<4 x double> %p)
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define <4 x double> @trunc_v4f64(<4 x double> %p)
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@ -67,10 +67,10 @@ define <4 x double> @trunc_v4f64(<4 x double> %p)
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ret <4 x double> %t
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}
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; CHECK: trunc_v4f64:
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; CHECK: bl trunc
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; CHECK: bl trunc
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; CHECK: bl trunc
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; CHECK: bl trunc
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; CHECK: friz
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; CHECK: friz
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; CHECK: friz
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; CHECK: friz
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declare <2 x double> @llvm.nearbyint.v2f64(<2 x double> %p)
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define <2 x double> @nearbyint_v2f64(<2 x double> %p)
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