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Add a transform to DAG Combiner. This improves the

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code for the case where 32-bit divide by constant is
turned into 64-bit multiply by constant.  8771012.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122090 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dale Johannesen
2010-12-17 21:45:49 +00:00
parent 48c166bceb
commit f5daf8bb7f
2 changed files with 29 additions and 0 deletions
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20
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -3171,6 +3171,26 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
DAG.getConstant(c1 + c2, N1.getValueType()));
}
// fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2)))
// This is only valid if the OpSizeInBits + c1 = size of inner shift
if (N1C && N0.getOpcode() == ISD::TRUNCATE &&
N0.getOperand(0).getOpcode() == ISD::SRL &&
N0.getOperand(0)->getOperand(1).getOpcode() == ISD::Constant) {
uint64_t c1 =
cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
uint64_t c2 = N1C->getZExtValue();
EVT InnerShiftVT = N0.getOperand(0)->getOperand(1).getValueType();
uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
if (c1 + OpSizeInBits == InnerShiftSize) {
if (c1 + c2 >= InnerShiftSize)
return DAG.getConstant(0, VT);
return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT,
DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT,
N0.getOperand(0)->getOperand(0),
DAG.getConstant(c1 + c2, InnerShiftVT)));
}
}
// fold (srl (shl x, c), c) -> (and x, cst2)
if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 &&
N0.getValueSizeInBits() <= 64) {