diff --git a/include/llvm/CodeGen/SelectionDAG.h b/include/llvm/CodeGen/SelectionDAG.h index f1a14bd3ff5..93df6ef17f3 100644 --- a/include/llvm/CodeGen/SelectionDAG.h +++ b/include/llvm/CodeGen/SelectionDAG.h @@ -648,41 +648,21 @@ public: /// Note that getTargetNode returns the resultant node. If there is already a /// node of the specified opcode and operands, it returns that node instead of /// the current one. - SDNode *getTargetNode(unsigned Opcode, MVT VT); SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT); - - SDNode *getTargetNode(unsigned Opcode, MVT VT, SDValue Op1); SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, SDValue Op1); - - SDNode *getTargetNode(unsigned Opcode, MVT VT, SDValue Op1, SDValue Op2); SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, SDValue Op1, SDValue Op2); - - SDNode *getTargetNode(unsigned Opcode, MVT VT, - SDValue Op1, SDValue Op2, SDValue Op3); SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, SDValue Op1, SDValue Op2, SDValue Op3); - SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, const SDValue *Ops, unsigned NumOps); - - SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2); SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2); - - SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, SDValue Op1); SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, SDValue Op1); - - SDNode *getTargetNode(unsigned Opcode, MVT VT1, - MVT VT2, SDValue Op1, SDValue Op2); SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, SDValue Op1, SDValue Op2); - - SDNode *getTargetNode(unsigned Opcode, MVT VT1, - MVT VT2, SDValue Op1, SDValue Op2, SDValue Op3); SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, SDValue Op1, SDValue Op2, SDValue Op3); - SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, const SDValue *Ops, unsigned NumOps); SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, MVT VT3, diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 770955a8f6b..581bdef08f6 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -4413,35 +4413,20 @@ SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, /// Note that getTargetNode returns the resultant node. If there is already a /// node of the specified opcode and operands, it returns that node instead of /// the current one. -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT) { - return getNode(~Opcode, VT).getNode(); -} SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT) { return getNode(~Opcode, dl, VT).getNode(); } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, SDValue Op1) { - return getNode(~Opcode, VT, Op1).getNode(); -} SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, SDValue Op1) { return getNode(~Opcode, dl, VT, Op1).getNode(); } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, - SDValue Op1, SDValue Op2) { - return getNode(~Opcode, VT, Op1, Op2).getNode(); -} SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, SDValue Op1, SDValue Op2) { return getNode(~Opcode, dl, VT, Op1, Op2).getNode(); } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, - SDValue Op1, SDValue Op2, - SDValue Op3) { - return getNode(~Opcode, VT, Op1, Op2, Op3).getNode(); -} SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, SDValue Op1, SDValue Op2, SDValue Op3) { @@ -4453,11 +4438,6 @@ SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, return getNode(~Opcode, dl, VT, Ops, NumOps).getNode(); } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2) { - const MVT *VTs = getNodeValueTypes(VT1, VT2); - SDValue Op; - return getNode(~Opcode, VTs, 2, &Op, 0).getNode(); -} SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2) { const MVT *VTs = getNodeValueTypes(VT1, VT2); @@ -4465,24 +4445,12 @@ SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, return getNode(~Opcode, dl, VTs, 2, &Op, 0).getNode(); } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, - MVT VT2, SDValue Op1) { - const MVT *VTs = getNodeValueTypes(VT1, VT2); - return getNode(~Opcode, VTs, 2, &Op1, 1).getNode(); -} SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, SDValue Op1) { const MVT *VTs = getNodeValueTypes(VT1, VT2); return getNode(~Opcode, dl, VTs, 2, &Op1, 1).getNode(); } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, - MVT VT2, SDValue Op1, - SDValue Op2) { - const MVT *VTs = getNodeValueTypes(VT1, VT2); - SDValue Ops[] = { Op1, Op2 }; - return getNode(~Opcode, VTs, 2, Ops, 2).getNode(); -} SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, SDValue Op1, SDValue Op2) { @@ -4491,13 +4459,6 @@ SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, return getNode(~Opcode, dl, VTs, 2, Ops, 2).getNode(); } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, - MVT VT2, SDValue Op1, - SDValue Op2, SDValue Op3) { - const MVT *VTs = getNodeValueTypes(VT1, VT2); - SDValue Ops[] = { Op1, Op2, Op3 }; - return getNode(~Opcode, VTs, 2, Ops, 3).getNode(); -} SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, SDValue Op1, SDValue Op2, SDValue Op3) { diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp index f79a84236ba..f45accc4f3e 100644 --- a/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -379,13 +379,15 @@ bool ARMDAGToDAGISel::SelectAddrModePC(SDValue Op, SDValue N, bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue Op, SDValue N, SDValue &Base, SDValue &Offset){ + // FIXME dl should come from the parent load or store, not the address + DebugLoc dl = Op.getDebugLoc(); if (N.getOpcode() != ISD::ADD) { Base = N; // We must materialize a zero in a reg! Returning a constant here // wouldn't work without additional code to position the node within // ISel's topological ordering in a place where ISel will process it // normally. Instead, just explicitly issue a tMOVri8 node! - Offset = SDValue(CurDAG->getTargetNode(ARM::tMOVi8, MVT::i32, + Offset = SDValue(CurDAG->getTargetNode(ARM::tMOVi8, dl, MVT::i32, CurDAG->getTargetConstant(0, MVT::i32)), 0); return true; } diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index f7744955b81..051fa8ce0cd 100644 --- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -98,7 +98,7 @@ namespace { /// SelectCC - Select a comparison of the specified values with the /// specified condition code, returning the CR# of the expression. - SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC); + SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, DebugLoc dl); /// SelectAddrImm - Returns true if the address N can be represented by /// a base register plus a signed 16-bit displacement [r+imm]. @@ -489,7 +489,7 @@ SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) { /// SelectCC - Select a comparison of the specified values with the specified /// condition code, returning the CR# of the expression. SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS, - ISD::CondCode CC) { + ISD::CondCode CC, DebugLoc dl) { // Always select the LHS. unsigned Opc; @@ -499,11 +499,11 @@ SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS, if (isInt32Immediate(RHS, Imm)) { // SETEQ/SETNE comparison with 16-bit immediate, fold it. if (isUInt16(Imm)) - return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, LHS, + return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, dl, MVT::i32, LHS, getI32Imm(Imm & 0xFFFF)), 0); // If this is a 16-bit signed immediate, fold it. if (isInt16((int)Imm)) - return SDValue(CurDAG->getTargetNode(PPC::CMPWI, MVT::i32, LHS, + return SDValue(CurDAG->getTargetNode(PPC::CMPWI, dl, MVT::i32, LHS, getI32Imm(Imm & 0xFFFF)), 0); // For non-equality comparisons, the default code would materialize the @@ -515,21 +515,21 @@ SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS, // xoris r0,r3,0x1234 // cmplwi cr0,r0,0x5678 // beq cr0,L6 - SDValue Xor(CurDAG->getTargetNode(PPC::XORIS, MVT::i32, LHS, + SDValue Xor(CurDAG->getTargetNode(PPC::XORIS, dl, MVT::i32, LHS, getI32Imm(Imm >> 16)), 0); - return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, Xor, + return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, dl, MVT::i32, Xor, getI32Imm(Imm & 0xFFFF)), 0); } Opc = PPC::CMPLW; } else if (ISD::isUnsignedIntSetCC(CC)) { if (isInt32Immediate(RHS, Imm) && isUInt16(Imm)) - return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, LHS, + return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, dl, MVT::i32, LHS, getI32Imm(Imm & 0xFFFF)), 0); Opc = PPC::CMPLW; } else { short SImm; if (isIntS16Immediate(RHS, SImm)) - return SDValue(CurDAG->getTargetNode(PPC::CMPWI, MVT::i32, LHS, + return SDValue(CurDAG->getTargetNode(PPC::CMPWI, dl, MVT::i32, LHS, getI32Imm((int)SImm & 0xFFFF)), 0); Opc = PPC::CMPW; @@ -540,11 +540,11 @@ SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS, if (isInt64Immediate(RHS.getNode(), Imm)) { // SETEQ/SETNE comparison with 16-bit immediate, fold it. if (isUInt16(Imm)) - return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, LHS, + return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, dl, MVT::i64, LHS, getI32Imm(Imm & 0xFFFF)), 0); // If this is a 16-bit signed immediate, fold it. if (isInt16(Imm)) - return SDValue(CurDAG->getTargetNode(PPC::CMPDI, MVT::i64, LHS, + return SDValue(CurDAG->getTargetNode(PPC::CMPDI, dl, MVT::i64, LHS, getI32Imm(Imm & 0xFFFF)), 0); // For non-equality comparisons, the default code would materialize the @@ -557,22 +557,22 @@ SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS, // cmpldi cr0,r0,0x5678 // beq cr0,L6 if (isUInt32(Imm)) { - SDValue Xor(CurDAG->getTargetNode(PPC::XORIS8, MVT::i64, LHS, + SDValue Xor(CurDAG->getTargetNode(PPC::XORIS8, dl, MVT::i64, LHS, getI64Imm(Imm >> 16)), 0); - return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, Xor, + return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, dl, MVT::i64, Xor, getI64Imm(Imm & 0xFFFF)), 0); } } Opc = PPC::CMPLD; } else if (ISD::isUnsignedIntSetCC(CC)) { if (isInt64Immediate(RHS.getNode(), Imm) && isUInt16(Imm)) - return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, LHS, + return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, dl, MVT::i64, LHS, getI64Imm(Imm & 0xFFFF)), 0); Opc = PPC::CMPLD; } else { short SImm; if (isIntS16Immediate(RHS, SImm)) - return SDValue(CurDAG->getTargetNode(PPC::CMPDI, MVT::i64, LHS, + return SDValue(CurDAG->getTargetNode(PPC::CMPDI, dl, MVT::i64, LHS, getI64Imm(SImm & 0xFFFF)), 0); Opc = PPC::CMPD; @@ -583,7 +583,7 @@ SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS, assert(LHS.getValueType() == MVT::f64 && "Unknown vt!"); Opc = PPC::FCMPUD; } - return SDValue(CurDAG->getTargetNode(Opc, MVT::i32, LHS, RHS), 0); + return SDValue(CurDAG->getTargetNode(Opc, dl, MVT::i32, LHS, RHS), 0); } static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) { @@ -729,7 +729,7 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDValue Op) { bool Inv; int OtherCondIdx; unsigned Idx = getCRIdxForSetCC(CC, Inv, OtherCondIdx); - SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC); + SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl); SDValue IntCR; // Force the ccreg into CR7. @@ -1057,7 +1057,7 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) { SDValue(Tmp, 1)); } - SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC); + SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl); unsigned BROpc = getPredicateForSetCC(CC); unsigned SelectCCOp; @@ -1091,7 +1091,7 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) { } case ISD::BR_CC: { ISD::CondCode CC = cast(N->getOperand(1))->get(); - SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC); + SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl); SDValue Ops[] = { getI32Imm(getPredicateForSetCC(CC)), CondCode, N->getOperand(4), N->getOperand(0) }; return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 4); diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 9099e757e7f..3d6b11bd0b0 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -815,6 +815,8 @@ bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base, bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG) const { + // FIXME dl should come from parent load or store, not from address + DebugLoc dl = N.getDebugLoc(); // If this can be more profitably realized as r+r, fail. if (SelectAddressRegReg(N, Disp, Base, DAG)) return false; @@ -882,7 +884,7 @@ bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp, Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32); unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; - Base = SDValue(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0); + Base = SDValue(DAG.getTargetNode(Opc, dl, CN->getValueType(0), Base), 0); return true; } } @@ -927,6 +929,8 @@ bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base, bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG) const { + // FIXME dl should come from the parent load or store, not the address + DebugLoc dl = N.getDebugLoc(); // If this can be more profitably realized as r+r, fail. if (SelectAddressRegReg(N, Disp, Base, DAG)) return false; @@ -990,10 +994,9 @@ bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp, // Otherwise, break this down into an LIS + disp. Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32); - Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32); unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; - Base = SDValue(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0); + Base = SDValue(DAG.getTargetNode(Opc, dl, CN->getValueType(0), Base),0); return true; } } diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp index 12ed94cba6d..c9bd62d0e20 100644 --- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp +++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp @@ -141,6 +141,7 @@ bool SparcDAGToDAGISel::SelectADDRrr(SDValue Op, SDValue Addr, SDNode *SparcDAGToDAGISel::Select(SDValue Op) { SDNode *N = Op.getNode(); + DebugLoc dl = N->getDebugLoc(); if (N->isMachineOpcode()) return NULL; // Already selected. @@ -155,12 +156,12 @@ SDNode *SparcDAGToDAGISel::Select(SDValue Op) { // Set the Y register to the high-part. SDValue TopPart; if (N->getOpcode() == ISD::SDIV) { - TopPart = SDValue(CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS, + TopPart = SDValue(CurDAG->getTargetNode(SP::SRAri, dl, MVT::i32, DivLHS, CurDAG->getTargetConstant(31, MVT::i32)), 0); } else { TopPart = CurDAG->getRegister(SP::G0, MVT::i32); } - TopPart = SDValue(CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart, + TopPart = SDValue(CurDAG->getTargetNode(SP::WRYrr, dl, MVT::Flag, TopPart, CurDAG->getRegister(SP::G0, MVT::i32)), 0); // FIXME: Handle div by immediate. @@ -174,7 +175,7 @@ SDNode *SparcDAGToDAGISel::Select(SDValue Op) { SDValue MulLHS = N->getOperand(0); SDValue MulRHS = N->getOperand(1); unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr; - SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag, + SDNode *Mul = CurDAG->getTargetNode(Opcode, dl, MVT::i32, MVT::Flag, MulLHS, MulRHS); // The high part is in the Y register. return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDValue(Mul, 1));