mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-19 20:34:38 +00:00
ppc long double. Implement fabs and fneg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42924 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
1c5d83c14e
commit
f646774edd
@ -6001,6 +6001,16 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
|
||||
break;
|
||||
}
|
||||
case ISD::FABS: {
|
||||
if (VT == MVT::ppcf128) {
|
||||
SDOperand Tmp;
|
||||
ExpandOp(Node->getOperand(0), Lo, Tmp);
|
||||
Hi = DAG.getNode(ISD::FABS, NVT, Tmp);
|
||||
// lo = hi==fabs(hi) ? lo : -lo;
|
||||
Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp,
|
||||
Lo, DAG.getNode(ISD::FNEG, NVT, Lo),
|
||||
DAG.getCondCode(ISD::SETEQ));
|
||||
break;
|
||||
}
|
||||
SDOperand Mask = (VT == MVT::f64)
|
||||
? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
|
||||
: DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
|
||||
@ -6012,6 +6022,12 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
|
||||
break;
|
||||
}
|
||||
case ISD::FNEG: {
|
||||
if (VT == MVT::ppcf128) {
|
||||
ExpandOp(Node->getOperand(0), Lo, Hi);
|
||||
Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo);
|
||||
Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi);
|
||||
break;
|
||||
}
|
||||
SDOperand Mask = (VT == MVT::f64)
|
||||
? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
|
||||
: DAG.getConstantFP(BitsToFloat(1U << 31), VT);
|
||||
|
Loading…
x
Reference in New Issue
Block a user