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ARM push of a single register encodes as pre-indexed STR.
Per the ARM ARM, a 'push' of a single register encodes as an STR, not an STM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137318 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2879,6 +2879,22 @@ processInstruction(MCInst &Inst,
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Inst = TmpInst;
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}
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break;
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case ARM::STMDB_UPD:
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// If this is a store of a single register via a 'push', then we should use
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// a pre-indexed STR instruction instead, per the ARM ARM.
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if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
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Inst.getNumOperands() == 5) {
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MCInst TmpInst;
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TmpInst.setOpcode(ARM::STR_PRE_IMM);
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TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
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TmpInst.addOperand(Inst.getOperand(4)); // Rt
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TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
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TmpInst.addOperand(MCOperand::CreateImm(-4));
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TmpInst.addOperand(Inst.getOperand(2)); // CondCode
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TmpInst.addOperand(Inst.getOperand(3));
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Inst = TmpInst;
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}
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break;
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}
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}
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@ -88,6 +88,13 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
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printRegisterList(MI, 4, O);
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return;
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}
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if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &&
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MI->getOperand(3).getImm() == -4) {
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O << '\t' << "push";
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printPredicateOperand(MI, 4, O);
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O << "\t{" << getRegisterName(MI->getOperand(1).getReg()) << "}";
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return;
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}
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// A8.6.122 POP
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if ((Opcode == ARM::LDMIA_UPD || Opcode == ARM::t2LDMIA_UPD) &&
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@ -7,7 +7,7 @@
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define i64 @t(i64 %a) nounwind readonly {
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entry:
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; CHECK: str lr, [sp, #-4]!
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; CHECK: push {lr}
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; CHECK: pop {lr}
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%0 = load i64** @b, align 4
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%1 = load i64* %0, align 4
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@ -1071,8 +1071,7 @@ Lforward:
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push {r7}
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push {r7, r8, r9, r10}
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@ FIXME: push of a single register should encode as "str r7, [sp, #-4]!"
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@ CHECK-FIXME: push {r7} @ encoding: [0x04,0x70,0x2d,0xe5]
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@ CHECK: push {r7} @ encoding: [0x04,0x70,0x2d,0xe5]
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@ CHECK: push {r7, r8, r9, r10} @ encoding: [0x80,0x07,0x2d,0xe9]
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