6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-26 21:32:10 +00:00
Code Issues Projects Releases Wiki Activity

With PPC CR bit registers, handle int_to_fp on older cores

Browse Source 
On cores without fpcvt support, we cannot promote int_to_fp i1 operations,
because there is nothing to promote them to. The most straightforward
implementation of this uses a select to choose between the two possible
resulting floating-point values (and that's what is done here).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203015 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel 2014-03-05 22:14:00 +00:00
parent af0cc459bf
commit f698d7775a
2 changed files with 37 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -100,12 +100,17 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
if (Subtarget->useCRBits()) { if (Subtarget->useCRBits()) {
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote); if (isPPC64 || Subtarget->hasFPCVT()) {
AddPromotedToType (ISD::SINT_TO_FP, MVT::i1, setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
isPPC64 ? MVT::i64 : MVT::i32); AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote); isPPC64 ? MVT::i64 : MVT::i32);
AddPromotedToType (ISD::UINT_TO_FP, MVT::i1, setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
isPPC64 ? MVT::i64 : MVT::i32); AddPromotedToType (ISD::UINT_TO_FP, MVT::i1,
isPPC64 ? MVT::i64 : MVT::i32);
} else {
setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
}
// PowerPC does not support direct load / store of condition registers // PowerPC does not support direct load / store of condition registers
setOperationAction(ISD::LOAD, MVT::i1, Custom); setOperationAction(ISD::LOAD, MVT::i1, Custom);
@ -4972,6 +4977,11 @@ SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64) if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
return SDValue(); return SDValue();
if (Op.getOperand(0).getValueType() == MVT::i1)
return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
DAG.getConstantFP(1.0, Op.getValueType()),
DAG.getConstantFP(0.0, Op.getValueType()));
assert((Op.getOpcode() == ISD::SINT_TO_FP || PPCSubTarget.hasFPCVT()) && assert((Op.getOpcode() == ISD::SINT_TO_FP || PPCSubTarget.hasFPCVT()) &&
"UINT_TO_FP is supported only with FPCVT"); "UINT_TO_FP is supported only with FPCVT");

21
test/CodeGen/PowerPC/i1-to-double.ll Normal file
View File

@ -0,0 +1,21 @@
; RUN: llc -march=ppc32 -mcpu=ppc32 -mtriple=powerpc-unknown-linux-gnu < %s | FileCheck %s
define double @test(i1 %X) {
%Y = uitofp i1 %X to double
ret double %Y
}
; CHECK-LABEL: @test
; CHECK: andi. {{[0-9]+}}, 3, 1
; CHECK: bc 12, 1,
; CHECK: li 3, .LCP[[L1:[A-Z0-9_]+]]@l
; CHECK: addis 3, 3, .LCP[[L1]]@ha
; CHECK: lfs 1, 0(3)
; CHECK: blr
; CHECK: li 3, .LCP[[L2:[A-Z0-9_]+]]@l
; CHECK: addis 3, 3, .LCP[[L2]]@ha
; CHECK: lfs 1, 0(3)
; CHECK: blr