mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-02-11 11:34:02 +00:00
Removing more special cases from LegalizeDAG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72465 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eli Friedman
parent
26ea8f982f
commit
f6f20a7779
@ -943,42 +943,6 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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}
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}
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break;
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case ISD::ConstantFP: {
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// Spill FP immediates to the constant pool if the target cannot directly
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// codegen them. Targets often have some immediate values that can be
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// efficiently generated into an FP register without a load. We explicitly
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// leave these constants as ConstantFP nodes for the target to deal with.
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ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
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switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
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default: assert(0 && "This action is not supported yet!");
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case TargetLowering::Legal:
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break;
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case TargetLowering::Custom:
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Tmp3 = TLI.LowerOperation(Result, DAG);
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if (Tmp3.getNode()) {
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Result = Tmp3;
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break;
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}
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// FALLTHROUGH
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case TargetLowering::Expand: {
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// Check to see if this FP immediate is already legal.
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bool isLegal = false;
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for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
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E = TLI.legal_fpimm_end(); I != E; ++I) {
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if (CFP->isExactlyValue(*I)) {
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isLegal = true;
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break;
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}
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}
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// If this is a legal constant, turn it into a TargetConstantFP node.
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if (isLegal)
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break;
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Result = ExpandConstantFP(CFP, true, DAG, TLI);
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}
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}
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break;
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}
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case ISD::FORMAL_ARGUMENTS:
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case ISD::CALL:
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// The only option for this is to custom lower it.
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@ -1321,42 +1285,6 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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}
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}
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break;
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case ISD::BRCOND:
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Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
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// Ensure that libcalls are emitted before a return.
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Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
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Tmp1 = LegalizeOp(Tmp1);
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LastCALLSEQ_END = DAG.getEntryNode();
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Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
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// Basic block destination (Op#2) is always legal.
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Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
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switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
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default: assert(0 && "This action is not supported yet!");
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case TargetLowering::Legal: break;
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case TargetLowering::Custom:
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Tmp1 = TLI.LowerOperation(Result, DAG);
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if (Tmp1.getNode()) Result = Tmp1;
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break;
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case TargetLowering::Expand:
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// Expand brcond's setcc into its constituent parts and create a BR_CC
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// Node.
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if (Tmp2.getOpcode() == ISD::SETCC) {
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Result = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
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Tmp1, Tmp2.getOperand(2),
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Tmp2.getOperand(0), Tmp2.getOperand(1),
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Node->getOperand(2));
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} else {
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Result = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
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DAG.getCondCode(ISD::SETNE), Tmp2,
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DAG.getConstant(0, Tmp2.getValueType()),
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Node->getOperand(2));
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}
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break;
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}
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break;
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case ISD::BR_CC:
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Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
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// Ensure that libcalls are emitted before a branch.
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@ -2039,104 +1967,6 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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}
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}
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break;
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case ISD::BUILD_PAIR: {
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MVT PairTy = Node->getValueType(0);
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// TODO: handle the case where the Lo and Hi operands are not of legal type
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Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
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Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
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switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
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case TargetLowering::Promote:
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case TargetLowering::Custom:
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assert(0 && "Cannot promote/custom this yet!");
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case TargetLowering::Legal:
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if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
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Result = DAG.getNode(ISD::BUILD_PAIR, dl, PairTy, Tmp1, Tmp2);
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break;
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case TargetLowering::Expand:
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Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Tmp1);
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Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Tmp2);
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Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
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DAG.getConstant(PairTy.getSizeInBits()/2,
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TLI.getShiftAmountTy()));
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Result = DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2);
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break;
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}
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break;
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}
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case ISD::UREM:
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case ISD::SREM:
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Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
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Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
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switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
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case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
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case TargetLowering::Custom:
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isCustom = true;
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// FALLTHROUGH
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case TargetLowering::Legal:
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Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
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if (isCustom) {
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Tmp1 = TLI.LowerOperation(Result, DAG);
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if (Tmp1.getNode()) Result = Tmp1;
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}
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break;
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case TargetLowering::Expand: {
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unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
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bool isSigned = DivOpc == ISD::SDIV;
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MVT VT = Node->getValueType(0);
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// See if remainder can be lowered using two-result operations.
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SDVTList VTs = DAG.getVTList(VT, VT);
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if (Node->getOpcode() == ISD::SREM &&
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TLI.isOperationLegalOrCustom(ISD::SDIVREM, VT)) {
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Result = SDValue(DAG.getNode(ISD::SDIVREM, dl,
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VTs, Tmp1, Tmp2).getNode(), 1);
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break;
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}
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if (Node->getOpcode() == ISD::UREM &&
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TLI.isOperationLegalOrCustom(ISD::UDIVREM, VT)) {
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Result = SDValue(DAG.getNode(ISD::UDIVREM, dl,
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VTs, Tmp1, Tmp2).getNode(), 1);
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break;
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}
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if (VT.isInteger() &&
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TLI.getOperationAction(DivOpc, VT) == TargetLowering::Legal) {
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// X % Y -> X-X/Y*Y
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Result = DAG.getNode(DivOpc, dl, VT, Tmp1, Tmp2);
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Result = DAG.getNode(ISD::MUL, dl, VT, Result, Tmp2);
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Result = DAG.getNode(ISD::SUB, dl, VT, Tmp1, Result);
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break;
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}
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// Check to see if we have a libcall for this operator.
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RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
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switch (Node->getOpcode()) {
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default: break;
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case ISD::UREM:
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case ISD::SREM:
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if (VT == MVT::i16)
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LC = (isSigned ? RTLIB::SREM_I16 : RTLIB::UREM_I16);
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else if (VT == MVT::i32)
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LC = (isSigned ? RTLIB::SREM_I32 : RTLIB::UREM_I32);
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else if (VT == MVT::i64)
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LC = (isSigned ? RTLIB::SREM_I64 : RTLIB::UREM_I64);
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else if (VT == MVT::i128)
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LC = (isSigned ? RTLIB::SREM_I128 : RTLIB::UREM_I128);
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break;
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}
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if (LC != RTLIB::UNKNOWN_LIBCALL) {
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Result = ExpandLibCall(LC, Node, isSigned);
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break;
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}
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assert(0 && "Cannot expand this binary operator!");
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break;
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}
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}
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break;
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case ISD::VAARG: {
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Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
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Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
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@ -3295,6 +3125,24 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
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RTLIB::REM_F80, RTLIB::REM_PPCF128));
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break;
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case ISD::ConstantFP: {
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ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
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// Check to see if this FP immediate is already legal.
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bool isLegal = false;
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for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
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E = TLI.legal_fpimm_end(); I != E; ++I) {
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if (CFP->isExactlyValue(*I)) {
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isLegal = true;
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break;
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}
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}
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// If this is a legal constant, turn it into a TargetConstantFP node.
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if (isLegal)
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Results.push_back(SDValue(Node, 0));
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else
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Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI));
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break;
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}
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case ISD::EHSELECTION: {
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unsigned Reg = TLI.getExceptionSelectorRegister();
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assert(Reg && "Can't expand to unknown register!");
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@ -3322,37 +3170,47 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
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break;
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}
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case ISD::UDIV:
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case ISD::UREM: {
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bool isRem = Node->getOpcode() == ISD::UREM;
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case ISD::UREM:
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case ISD::SREM: {
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MVT VT = Node->getValueType(0);
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SDVTList VTs = DAG.getVTList(VT, VT);
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if (TLI.isOperationLegalOrCustom(ISD::UDIVREM, VT))
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Tmp1 = DAG.getNode(ISD::UDIVREM, dl, VTs, Node->getOperand(0),
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Node->getOperand(1)).getValue(isRem);
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else if (isRem)
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bool isSigned = Node->getOpcode() == ISD::SREM;
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unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
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unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
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Tmp2 = Node->getOperand(0);
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Tmp3 = Node->getOperand(1);
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if (TLI.getOperationAction(DivOpc, VT) == TargetLowering::Legal) {
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// X % Y -> X-X/Y*Y
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Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
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Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
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Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
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} else if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) {
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Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
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} else if (isSigned) {
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Tmp1 = ExpandIntLibCall(Node, true, RTLIB::SREM_I16, RTLIB::SREM_I32,
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RTLIB::SREM_I64, RTLIB::SREM_I128);
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} else {
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Tmp1 = ExpandIntLibCall(Node, false, RTLIB::UREM_I16, RTLIB::UREM_I32,
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RTLIB::UREM_I64, RTLIB::UREM_I128);
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else
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Tmp1 = ExpandIntLibCall(Node, false, RTLIB::UDIV_I16, RTLIB::UDIV_I32,
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RTLIB::UDIV_I64, RTLIB::UDIV_I128);
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}
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Results.push_back(Tmp1);
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break;
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}
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case ISD::SDIV:
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case ISD::SREM: {
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bool isRem = Node->getOpcode() == ISD::SREM;
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case ISD::UDIV:
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case ISD::SDIV: {
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bool isSigned = Node->getOpcode() == ISD::SDIV;
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unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
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MVT VT = Node->getValueType(0);
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SDVTList VTs = DAG.getVTList(VT, VT);
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if (TLI.isOperationLegalOrCustom(ISD::SDIVREM, VT))
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Tmp1 = DAG.getNode(ISD::SDIVREM, dl, VTs, Node->getOperand(0),
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Node->getOperand(1)).getValue(isRem);
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else if (isRem)
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Tmp1 = ExpandIntLibCall(Node, true, RTLIB::SREM_I16, RTLIB::SREM_I32,
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RTLIB::SREM_I64, RTLIB::SREM_I128);
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else
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if (TLI.isOperationLegalOrCustom(DivRemOpc, VT))
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Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
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Node->getOperand(1));
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else if (isSigned)
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Tmp1 = ExpandIntLibCall(Node, true, RTLIB::SDIV_I16, RTLIB::SDIV_I32,
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RTLIB::SDIV_I64, RTLIB::SDIV_I128);
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else
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Tmp1 = ExpandIntLibCall(Node, false, RTLIB::UDIV_I16, RTLIB::UDIV_I32,
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RTLIB::UDIV_I64, RTLIB::UDIV_I128);
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Results.push_back(Tmp1);
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break;
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}
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@ -3392,7 +3250,8 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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OpToUse = ISD::UMUL_LOHI;
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}
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if (OpToUse) {
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Results.push_back(DAG.getNode(OpToUse, dl, VTs, Tmp1, Tmp2));
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Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
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Node->getOperand(1)));
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break;
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}
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Tmp1 = ExpandIntLibCall(Node, false, RTLIB::MUL_I16, RTLIB::MUL_I32,
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@ -3400,6 +3259,34 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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Results.push_back(Tmp1);
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break;
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}
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case ISD::BUILD_PAIR: {
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MVT PairTy = Node->getValueType(0);
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Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
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Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
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Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
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DAG.getConstant(PairTy.getSizeInBits()/2,
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TLI.getShiftAmountTy()));
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Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
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break;
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}
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case ISD::BRCOND:
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// Expand brcond's setcc into its constituent parts and create a BR_CC
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// Node.
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Tmp1 = Node->getOperand(0);
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Tmp2 = Node->getOperand(1);
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if (Tmp2.getOpcode() == ISD::SETCC) {
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Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
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Tmp1, Tmp2.getOperand(2),
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Tmp2.getOperand(0), Tmp2.getOperand(1),
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Node->getOperand(2));
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} else {
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Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
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DAG.getCondCode(ISD::SETNE), Tmp2,
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DAG.getConstant(0, Tmp2.getValueType()),
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Node->getOperand(2));
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}
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Results.push_back(Tmp1);
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break;
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case ISD::GLOBAL_OFFSET_TABLE:
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case ISD::GlobalAddress:
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case ISD::GlobalTLSAddress:
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