From f73bae1b73211c77238f64029ee2bec7ce90bba2 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Tue, 29 Nov 2005 06:16:21 +0000 Subject: [PATCH] No targets support line number info yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24513 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Alpha/AlphaISelLowering.cpp | 3 +++ lib/Target/IA64/IA64ISelLowering.cpp | 3 +++ lib/Target/PowerPC/PPCISelLowering.cpp | 3 +++ lib/Target/X86/X86ISelLowering.cpp | 3 +++ 4 files changed, 12 insertions(+) diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp index df84d52feb5..021c92db3c9 100644 --- a/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/lib/Target/Alpha/AlphaISelLowering.cpp @@ -97,6 +97,9 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) //Doesn't work yet setOperationAction(ISD::SETCC, MVT::f32, Promote); + + // We don't have line number support yet. + setOperationAction(ISD::LOCATION, MVT::Other, Expand); computeRegisterProperties(); diff --git a/lib/Target/IA64/IA64ISelLowering.cpp b/lib/Target/IA64/IA64ISelLowering.cpp index d757496f1de..e7276d4698c 100644 --- a/lib/Target/IA64/IA64ISelLowering.cpp +++ b/lib/Target/IA64/IA64ISelLowering.cpp @@ -72,6 +72,9 @@ IA64TargetLowering::IA64TargetLowering(TargetMachine &TM) setOperationAction(ISD::FCOS , MVT::f32, Expand); setOperationAction(ISD::FSQRT, MVT::f32, Expand); + // We don't have line number support yet. + setOperationAction(ISD::LOCATION, MVT::Other, Expand); + //IA64 has these, but they are not implemented setOperationAction(ISD::CTTZ , MVT::i64 , Expand); setOperationAction(ISD::CTLZ , MVT::i64 , Expand); diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 6f798c38ed8..9526ae1f2a7 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -90,6 +90,9 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM) // PowerPC does not have truncstore for i1. setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote); + + // PowerPC doesn't have line number support yet. + setOperationAction(ISD::LOCATION, MVT::Other, Expand); // We want to legalize GlobalAddress into the appropriate instructions to // materialize the address. diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index d4de67f0972..b42faa0a095 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -116,6 +116,9 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM) setOperationAction(ISD::SELECT , MVT::i1 , Promote); setOperationAction(ISD::SELECT , MVT::i8 , Promote); + // We don't have line number support yet. + setOperationAction(ISD::LOCATION, MVT::Other, Expand); + if (X86ScalarSSE) { // Set up the FP register classes. addRegisterClass(MVT::f32, X86::V4F4RegisterClass);