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The Mips standalone assembler fpu instruction support.
Test cases included Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163363 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jack Carter
parent
307525cd24
commit
f740d6e328
@ -27,6 +27,14 @@ namespace {
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class MipsAsmParser : public MCTargetAsmParser {
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enum FpFormatTy {
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FP_FORMAT_NONE = -1,
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FP_FORMAT_S,
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FP_FORMAT_D,
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FP_FORMAT_L,
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FP_FORMAT_W
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} FpFormat;
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MCSubtargetInfo &STI;
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MCAsmParser &Parser;
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@ -42,6 +50,9 @@ class MipsAsmParser : public MCTargetAsmParser {
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bool ParseInstruction(StringRef Name, SMLoc NameLoc,
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SmallVectorImpl<MCParsedAsmOperand*> &Operands);
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bool parseMathOperation(StringRef Name, SMLoc NameLoc,
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SmallVectorImpl<MCParsedAsmOperand*> &Operands);
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bool ParseDirective(AsmToken DirectiveID);
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MipsAsmParser::OperandMatchResultTy
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@ -63,14 +74,31 @@ class MipsAsmParser : public MCTargetAsmParser {
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bool parseMemOffset(const MCExpr *&Res);
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bool parseRelocOperand(const MCExpr *&Res);
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MCSymbolRefExpr::VariantKind getVariantKind(StringRef Symbol);
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bool isMips64() const {
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return (STI.getFeatureBits() & Mips::FeatureMips64) != 0;
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}
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bool isFP64() const {
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return (STI.getFeatureBits() & Mips::FeatureFP64Bit) != 0;
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}
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int matchRegisterName(StringRef Symbol);
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int matchRegisterByNumber(unsigned RegNum, StringRef Mnemonic);
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void setFpFormat(FpFormatTy Format) {
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FpFormat = Format;
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}
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void setDefaultFpFormat();
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void setFpFormat(StringRef Format);
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FpFormatTy getFpFormat() {return FpFormat;}
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bool requestsDoubleOperand(StringRef Mnemonic);
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unsigned getReg(int RC,int RegNo);
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public:
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@ -327,8 +355,59 @@ int MipsAsmParser::matchRegisterName(StringRef Name) {
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return CC;
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}
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if (Name[0] == 'f') {
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StringRef NumString = Name.substr(1);
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unsigned IntVal;
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if( NumString.getAsInteger(10, IntVal))
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return -1; //not integer
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if (IntVal > 31)
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return -1;
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FpFormatTy Format = getFpFormat();
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if (Format == FP_FORMAT_S || Format == FP_FORMAT_W)
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return getReg(Mips::FGR32RegClassID, IntVal);
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if (Format == FP_FORMAT_D) {
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if(isFP64()) {
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return getReg(Mips::FGR64RegClassID, IntVal);
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}
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//only even numbers available as register pairs
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if (( IntVal > 31) || (IntVal%2 != 0))
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return -1;
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return getReg(Mips::AFGR64RegClassID, IntVal/2);
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}
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}
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return -1;
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}
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void MipsAsmParser::setDefaultFpFormat() {
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if (isMips64() || isFP64())
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FpFormat = FP_FORMAT_D;
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else
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FpFormat = FP_FORMAT_S;
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}
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bool MipsAsmParser::requestsDoubleOperand(StringRef Mnemonic){
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bool IsDouble = StringSwitch<bool>(Mnemonic.lower())
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.Case("ldxc1", true)
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.Case("ldc1", true)
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.Case("sdxc1", true)
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.Case("sdc1", true)
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.Default(false);
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return IsDouble;
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}
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void MipsAsmParser::setFpFormat(StringRef Format) {
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FpFormat = StringSwitch<FpFormatTy>(Format.lower())
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.Case(".s", FP_FORMAT_S)
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.Case(".d", FP_FORMAT_D)
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.Case(".l", FP_FORMAT_L)
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.Case(".w", FP_FORMAT_W)
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.Default(FP_FORMAT_NONE);
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}
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unsigned MipsAsmParser::getReg(int RC,int RegNo){
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return *(getContext().getRegisterInfo().getRegClass(RC).begin() + RegNo);
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@ -359,6 +438,13 @@ int MipsAsmParser::tryParseRegister(StringRef Mnemonic) {
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} else if (Tok.is(AsmToken::Integer))
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RegNum = matchRegisterByNumber(static_cast<unsigned> (Tok.getIntVal()),
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Mnemonic.lower());
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else
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return RegNum; //error
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//64 bit div operations require Mips::ZERO instead of MIPS::ZERO_64
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if (isMips64() && RegNum == Mips::ZERO_64) {
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if (Mnemonic.find("ddiv") != StringRef::npos)
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RegNum = Mips::ZERO;
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}
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return RegNum;
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}
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@ -368,12 +454,21 @@ bool MipsAsmParser::
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SMLoc S = Parser.getTok().getLoc();
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int RegNo = -1;
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RegNo = tryParseRegister(Mnemonic);
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//FIXME: we should make a more generic method for CCR
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if ((Mnemonic == "cfc1" || Mnemonic == "ctc1")
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&& Operands.size() == 2 && Parser.getTok().is(AsmToken::Integer)){
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RegNo = Parser.getTok().getIntVal(); //get the int value
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//at the moment only fcc0 is supported
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if (RegNo == 0)
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RegNo = Mips::FCC0;
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} else
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RegNo = tryParseRegister(Mnemonic);
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if (RegNo == -1)
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return true;
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Operands.push_back(MipsOperand::CreateReg(RegNo, S,
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Parser.getTok().getLoc()));
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Parser.getTok().getLoc()));
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Parser.Lex(); // Eat register token.
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return false;
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}
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@ -550,9 +645,8 @@ bool MipsAsmParser::parseMemOffset(const MCExpr *&Res) {
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case AsmToken::Minus:
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case AsmToken::Plus:
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return (getParser().ParseExpression(Res));
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case AsmToken::Percent: {
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case AsmToken::Percent:
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return parseRelocOperand(Res);
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}
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case AsmToken::LParen:
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return false; //it's probably assuming 0
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}
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@ -641,12 +735,131 @@ MCSymbolRefExpr::VariantKind MipsAsmParser::getVariantKind(StringRef Symbol) {
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return VK;
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}
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int ConvertCcString(StringRef CondString){
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int CC = StringSwitch<unsigned>(CondString)
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.Case(".f", 0)
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.Case(".un", 1)
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.Case(".eq", 2)
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.Case(".ueq", 3)
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.Case(".olt", 4)
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.Case(".ult", 5)
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.Case(".ole", 6)
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.Case(".ule", 7)
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.Case(".sf", 8)
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.Case(".ngle", 9)
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.Case(".seq", 10)
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.Case(".ngl", 11)
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.Case(".lt", 12)
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.Case(".nge", 13)
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.Case(".le", 14)
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.Case(".ngt", 15)
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.Default(-1);
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return CC;
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}
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bool MipsAsmParser::
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parseMathOperation(StringRef Name, SMLoc NameLoc,
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SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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//split the format
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size_t Start = Name.find('.'), Next = Name.rfind('.');
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StringRef Format1 = Name.slice(Start, Next);
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//and add the first format to the operands
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Operands.push_back(MipsOperand::CreateToken(Format1, NameLoc));
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//now for the second format
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StringRef Format2 = Name.slice(Next, StringRef::npos);
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Operands.push_back(MipsOperand::CreateToken(Format2, NameLoc));
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//set the format for the first register
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setFpFormat(Format1);
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// Read the remaining operands.
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if (getLexer().isNot(AsmToken::EndOfStatement)) {
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// Read the first operand.
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if (ParseOperand(Operands, Name)) {
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SMLoc Loc = getLexer().getLoc();
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Parser.EatToEndOfStatement();
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return Error(Loc, "unexpected token in argument list");
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}
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if (getLexer().isNot(AsmToken::Comma)) {
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SMLoc Loc = getLexer().getLoc();
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Parser.EatToEndOfStatement();
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return Error(Loc, "unexpected token in argument list");
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}
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Parser.Lex(); // Eat the comma.
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//set the format for the first register
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setFpFormat(Format2);
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// Parse and remember the operand.
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if (ParseOperand(Operands, Name)) {
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SMLoc Loc = getLexer().getLoc();
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Parser.EatToEndOfStatement();
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return Error(Loc, "unexpected token in argument list");
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}
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}
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if (getLexer().isNot(AsmToken::EndOfStatement)) {
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SMLoc Loc = getLexer().getLoc();
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Parser.EatToEndOfStatement();
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return Error(Loc, "unexpected token in argument list");
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}
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Parser.Lex(); // Consume the EndOfStatement
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return false;
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}
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bool MipsAsmParser::
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ParseInstruction(StringRef Name, SMLoc NameLoc,
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SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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//first operand is a instruction mnemonic
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//floating point instructions: should register be treated as double?
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if (requestsDoubleOperand(Name)) {
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setFpFormat(FP_FORMAT_D);
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Operands.push_back(MipsOperand::CreateToken(Name, NameLoc));
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}
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else {
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setDefaultFpFormat();
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// Create the leading tokens for the mnemonic, split by '.' characters.
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size_t Start = 0, Next = Name.find('.');
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StringRef Mnemonic = Name.slice(Start, Next);
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Operands.push_back(MipsOperand::CreateToken(Mnemonic, NameLoc));
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if (Next != StringRef::npos) {
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//there is a format token in mnemonic
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//StringRef Rest = Name.slice(Next, StringRef::npos);
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size_t Dot = Name.find('.', Next+1);
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StringRef Format = Name.slice(Next, Dot);
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if (Dot == StringRef::npos) //only one '.' in a string, it's a format
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Operands.push_back(MipsOperand::CreateToken(Format, NameLoc));
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else {
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if (Name.startswith("c.")){
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// floating point compare, add '.' and immediate represent for cc
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Operands.push_back(MipsOperand::CreateToken(".", NameLoc));
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int Cc = ConvertCcString(Format);
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if (Cc == -1) {
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return Error(NameLoc, "Invalid conditional code");
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}
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SMLoc E = SMLoc::getFromPointer(
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Parser.getTok().getLoc().getPointer() -1 );
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Operands.push_back(MipsOperand::CreateImm(
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MCConstantExpr::Create(Cc, getContext()), NameLoc, E));
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} else {
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//trunc, ceil, floor ...
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return parseMathOperation(Name, NameLoc, Operands);
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}
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//the rest is a format
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Format = Name.slice(Dot, StringRef::npos);
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Operands.push_back(MipsOperand::CreateToken(Format, NameLoc));
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}
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setFpFormat(Format);
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}
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}
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// Read the remaining operands.
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if (getLexer().isNot(AsmToken::EndOfStatement)) {
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@ -122,7 +122,7 @@ inline static unsigned getMipsRegisterNumbering(unsigned RegEnum)
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{
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switch (RegEnum) {
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case Mips::ZERO: case Mips::ZERO_64: case Mips::F0: case Mips::D0_64:
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case Mips::D0:
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case Mips::D0: case Mips::FCC0:
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return 0;
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case Mips::AT: case Mips::AT_64: case Mips::F1: case Mips::D1_64:
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return 1;
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162
test/MC/Mips/mips-fpu-instructions.s
Normal file
162
test/MC/Mips/mips-fpu-instructions.s
Normal file
@ -0,0 +1,162 @@
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# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 | FileCheck %s
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# Check that the assembler can handle the documented syntax
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# for FPU instructions.
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# CHECK: .section __TEXT,__text,regular,pure_instructions
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#------------------------------------------------------------------------------
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# FP aritmetic instructions
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#------------------------------------------------------------------------------
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# CHECK: abs.d $f12, $f14 # encoding: [0x05,0x73,0x20,0x46]
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# CHECK: abs.s $f6, $f7 # encoding: [0x85,0x39,0x00,0x46]
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# CHECK: add.d $f8, $f12, $f14 # encoding: [0x00,0x62,0x2e,0x46]
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# CHECK: add.s $f9, $f6, $f7 # encoding: [0x40,0x32,0x07,0x46]
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# CHECK: floor.w.d $f12, $f14 # encoding: [0x0f,0x73,0x20,0x46]
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# CHECK: floor.w.s $f6, $f7 # encoding: [0x8f,0x39,0x00,0x46]
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# CHECK: ceil.w.d $f12, $f14 # encoding: [0x0e,0x73,0x20,0x46]
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# CHECK: ceil.w.s $f6, $f7 # encoding: [0x8e,0x39,0x00,0x46]
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# CHECK: mul.d $f8, $f12, $f14 # encoding: [0x02,0x62,0x2e,0x46]
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# CHECK: mul.s $f9, $f6, $f7 # encoding: [0x42,0x32,0x07,0x46]
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# CHECK: neg.d $f12, $f14 # encoding: [0x07,0x73,0x20,0x46]
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# CHECK: neg.s $f6, $f7 # encoding: [0x87,0x39,0x00,0x46]
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# CHECK: round.w.d $f12, $f14 # encoding: [0x0c,0x73,0x20,0x46]
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# CHECK: round.w.s $f6, $f7 # encoding: [0x8c,0x39,0x00,0x46]
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# CHECK: sqrt.d $f12, $f14 # encoding: [0x04,0x73,0x20,0x46]
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# CHECK: sqrt.s $f6, $f7 # encoding: [0x84,0x39,0x00,0x46]
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# CHECK: sub.d $f8, $f12, $f14 # encoding: [0x01,0x62,0x2e,0x46]
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# CHECK: sub.s $f9, $f6, $f7 # encoding: [0x41,0x32,0x07,0x46]
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# CHECK: trunc.w.d $f12, $f14 # encoding: [0x0d,0x73,0x20,0x46]
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# CHECK: trunc.w.s $f6, $f7 # encoding: [0x8d,0x39,0x00,0x46]
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abs.d $f12,$f14
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abs.s $f6,$f7
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add.d $f8,$f12,$f14
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add.s $f9,$f6,$f7
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floor.w.d $f12,$f14
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floor.w.s $f6,$f7
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ceil.w.d $f12,$f14
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ceil.w.s $f6,$f7
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mul.d $f8,$f12,$f14
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mul.s $f9,$f6, $f7
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neg.d $f12,$f14
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neg.s $f6,$f7
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round.w.d $f12,$f14
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round.w.s $f6,$f7
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sqrt.d $f12,$f14
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sqrt.s $f6,$f7
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sub.d $f8,$f12,$f14
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sub.s $f9,$f6,$f7
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trunc.w.d $f12,$f14
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trunc.w.s $f6,$f7
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#------------------------------------------------------------------------------
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# FP compare instructions
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#------------------------------------------------------------------------------
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# CHECK: c.eq.d $f12, $f14 # encoding: [0x32,0x60,0x2e,0x46]
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# CHECK: c.eq.s $f6, $f7 # encoding: [0x32,0x30,0x07,0x46]
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# CHECK: c.f.d $f12, $f14 # encoding: [0x30,0x60,0x2e,0x46]
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# CHECK: c.f.s $f6, $f7 # encoding: [0x30,0x30,0x07,0x46]
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# CHECK: c.le.d $f12, $f14 # encoding: [0x3e,0x60,0x2e,0x46]
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# CHECK: c.le.s $f6, $f7 # encoding: [0x3e,0x30,0x07,0x46]
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# CHECK: c.lt.d $f12, $f14 # encoding: [0x3c,0x60,0x2e,0x46]
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# CHECK: c.lt.s $f6, $f7 # encoding: [0x3c,0x30,0x07,0x46]
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# CHECK: c.nge.d $f12, $f14 # encoding: [0x3d,0x60,0x2e,0x46]
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# CHECK: c.nge.s $f6, $f7 # encoding: [0x3d,0x30,0x07,0x46]
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# CHECK: c.ngl.d $f12, $f14 # encoding: [0x3b,0x60,0x2e,0x46]
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# CHECK: c.ngl.s $f6, $f7 # encoding: [0x3b,0x30,0x07,0x46]
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# CHECK: c.ngle.d $f12, $f14 # encoding: [0x39,0x60,0x2e,0x46]
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# CHECK: c.ngle.s $f6, $f7 # encoding: [0x39,0x30,0x07,0x46]
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# CHECK: c.ngt.d $f12, $f14 # encoding: [0x3f,0x60,0x2e,0x46]
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# CHECK: c.ngt.s $f6, $f7 # encoding: [0x3f,0x30,0x07,0x46]
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# CHECK: c.ole.d $f12, $f14 # encoding: [0x36,0x60,0x2e,0x46]
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# CHECK: c.ole.s $f6, $f7 # encoding: [0x36,0x30,0x07,0x46]
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# CHECK: c.olt.d $f12, $f14 # encoding: [0x34,0x60,0x2e,0x46]
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# CHECK: c.olt.s $f6, $f7 # encoding: [0x34,0x30,0x07,0x46]
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# CHECK: c.seq.d $f12, $f14 # encoding: [0x3a,0x60,0x2e,0x46]
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# CHECK: c.seq.s $f6, $f7 # encoding: [0x3a,0x30,0x07,0x46]
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# CHECK: c.sf.d $f12, $f14 # encoding: [0x38,0x60,0x2e,0x46]
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# CHECK: c.sf.s $f6, $f7 # encoding: [0x38,0x30,0x07,0x46]
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# CHECK: c.ueq.d $f12, $f14 # encoding: [0x33,0x60,0x2e,0x46]
|
||||
# CHECK: c.ueq.s $f28, $f18 # encoding: [0x33,0xe0,0x12,0x46]
|
||||
# CHECK: c.ule.d $f12, $f14 # encoding: [0x37,0x60,0x2e,0x46]
|
||||
# CHECK: c.ule.s $f6, $f7 # encoding: [0x37,0x30,0x07,0x46]
|
||||
# CHECK: c.ult.d $f12, $f14 # encoding: [0x35,0x60,0x2e,0x46]
|
||||
# CHECK: c.ult.s $f6, $f7 # encoding: [0x35,0x30,0x07,0x46]
|
||||
# CHECK: c.un.d $f12, $f14 # encoding: [0x31,0x60,0x2e,0x46]
|
||||
# CHECK: c.un.s $f6, $f7 # encoding: [0x31,0x30,0x07,0x46]
|
||||
|
||||
c.eq.d $f12,$f14
|
||||
c.eq.s $f6,$f7
|
||||
c.f.d $f12,$f14
|
||||
c.f.s $f6,$f7
|
||||
c.le.d $f12,$f14
|
||||
c.le.s $f6,$f7
|
||||
c.lt.d $f12,$f14
|
||||
c.lt.s $f6,$f7
|
||||
c.nge.d $f12,$f14
|
||||
c.nge.s $f6,$f7
|
||||
c.ngl.d $f12,$f14
|
||||
c.ngl.s $f6,$f7
|
||||
c.ngle.d $f12,$f14
|
||||
c.ngle.s $f6,$f7
|
||||
c.ngt.d $f12,$f14
|
||||
c.ngt.s $f6,$f7
|
||||
c.ole.d $f12,$f14
|
||||
c.ole.s $f6,$f7
|
||||
c.olt.d $f12,$f14
|
||||
c.olt.s $f6,$f7
|
||||
c.seq.d $f12,$f14
|
||||
c.seq.s $f6,$f7
|
||||
c.sf.d $f12,$f14
|
||||
c.sf.s $f6,$f7
|
||||
c.ueq.d $f12,$f14
|
||||
c.ueq.s $f28,$f18
|
||||
c.ule.d $f12,$f14
|
||||
c.ule.s $f6,$f7
|
||||
c.ult.d $f12,$f14
|
||||
c.ult.s $f6,$f7
|
||||
c.un.d $f12,$f14
|
||||
c.un.s $f6,$f7
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
# FP convert instructions
|
||||
#------------------------------------------------------------------------------
|
||||
# CHECK: cvt.d.s $f6, $f7 # encoding: [0xa1,0x39,0x00,0x46]
|
||||
# CHECK: cvt.d.w $f12, $f14 # encoding: [0x21,0x73,0x80,0x46]
|
||||
# CHECK: cvt.s.d $f12, $f14 # encoding: [0x20,0x73,0x20,0x46]
|
||||
# CHECK: cvt.s.w $f6, $f7 # encoding: [0xa0,0x39,0x80,0x46]
|
||||
# CHECK: cvt.w.d $f12, $f14 # encoding: [0x24,0x73,0x20,0x46]
|
||||
# CHECK: cvt.w.s $f6, $f7 # encoding: [0xa4,0x39,0x00,0x46]
|
||||
|
||||
cvt.d.s $f6,$f7
|
||||
cvt.d.w $f12,$f14
|
||||
cvt.s.d $f12,$f14
|
||||
cvt.s.w $f6,$f7
|
||||
cvt.w.d $f12,$f14
|
||||
cvt.w.s $f6,$f7
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
# FP move instructions
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
# CHECK: cfc1 $6, $fcc0 # encoding: [0x00,0x00,0x46,0x44]
|
||||
# CHECK: mfc1 $6, $f7 # encoding: [0x00,0x38,0x06,0x44]
|
||||
# CHECK: mfhi $5 # encoding: [0x10,0x28,0x00,0x00]
|
||||
# CHECK: mflo $5 # encoding: [0x12,0x28,0x00,0x00]
|
||||
# CHECK: mov.d $f6, $f8 # encoding: [0x86,0x41,0x20,0x46]
|
||||
# CHECK: mov.s $f6, $f7 # encoding: [0x86,0x39,0x00,0x46]
|
||||
# CHECK: mtc1 $6, $f7 # encoding: [0x00,0x38,0x86,0x44]
|
||||
# CHECK: mthi $7 # encoding: [0x11,0x00,0xe0,0x00]
|
||||
# CHECK: mtlo $7 # encoding: [0x13,0x00,0xe0,0x00]
|
||||
# CHECK: swc1 $f9, 9158($7) # encoding: [0xc6,0x23,0xe9,0xe4]
|
||||
|
||||
cfc1 $a2,$0
|
||||
mfc1 $a2,$f7
|
||||
mfhi $a1
|
||||
mflo $a1
|
||||
mov.d $f6,$f8
|
||||
mov.s $f6,$f7
|
||||
mtc1 $a2,$f7
|
||||
mthi $a3
|
||||
mtlo $a3
|
||||
swc1 $f9,9158($a3)
|
||||
@ -10,11 +10,15 @@
|
||||
# CHECK: sh $4, 16($5) # encoding: [0x10,0x00,0xa4,0xa4]
|
||||
# CHECK: sw $4, 16($5) # encoding: [0x10,0x00,0xa4,0xac]
|
||||
# CHECK: sw $7, 0($5) # encoding: [0x00,0x00,0xa7,0xac]
|
||||
# CHECK: swc1 $f2, 16($5) # encoding: [0x10,0x00,0xa2,0xe4]
|
||||
# CHECK: swl $4, 16($5) # encoding: [0x10,0x00,0xa4,0xa8]
|
||||
sb $4, 16($5)
|
||||
sc $4, 16($5)
|
||||
sh $4, 16($5)
|
||||
sw $4, 16($5)
|
||||
sw $7, ($5)
|
||||
swc1 $f2, 16($5)
|
||||
swl $4, 16($5)
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
# Memory load instructions
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user