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Forgot 'svn add' again, sorry!
Tests for r186574. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186580 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Joey Gouly
parent
4e377d9306
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145
test/CodeGen/ARM/vcvt-v8.ll
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145
test/CodeGen/ARM/vcvt-v8.ll
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; RUN: llc < %s -mtriple=armv8 -mattr=+neon | FileCheck %s
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define <4 x i32> @vcvtasq(<4 x float>* %A) {
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; CHECK: vcvtasq
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; CHECK: vcvta.s32.f32 q{{[0-9]+}}, q{{[0-9]+}}
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%tmp1 = load <4 x float>* %A
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%tmp2 = call <4 x i32> @llvm.arm.neon.vcvtas.v4i32.v4f32(<4 x float> %tmp1)
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ret <4 x i32> %tmp2
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}
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define <2 x i32> @vcvtasd(<2 x float>* %A) {
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; CHECK: vcvtasd
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; CHECK: vcvta.s32.f32 d{{[0-9]+}}, d{{[0-9]+}}
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%tmp1 = load <2 x float>* %A
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%tmp2 = call <2 x i32> @llvm.arm.neon.vcvtas.v2i32.v2f32(<2 x float> %tmp1)
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ret <2 x i32> %tmp2
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}
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define <4 x i32> @vcvtnsq(<4 x float>* %A) {
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; CHECK: vcvtnsq
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; CHECK: vcvtn.s32.f32 q{{[0-9]+}}, q{{[0-9]+}}
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%tmp1 = load <4 x float>* %A
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%tmp2 = call <4 x i32> @llvm.arm.neon.vcvtns.v4i32.v4f32(<4 x float> %tmp1)
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ret <4 x i32> %tmp2
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}
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define <2 x i32> @vcvtnsd(<2 x float>* %A) {
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; CHECK: vcvtnsd
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; CHECK: vcvtn.s32.f32 d{{[0-9]+}}, d{{[0-9]+}}
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%tmp1 = load <2 x float>* %A
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%tmp2 = call <2 x i32> @llvm.arm.neon.vcvtns.v2i32.v2f32(<2 x float> %tmp1)
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ret <2 x i32> %tmp2
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}
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define <4 x i32> @vcvtpsq(<4 x float>* %A) {
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; CHECK: vcvtpsq
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; CHECK: vcvtp.s32.f32 q{{[0-9]+}}, q{{[0-9]+}}
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%tmp1 = load <4 x float>* %A
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%tmp2 = call <4 x i32> @llvm.arm.neon.vcvtps.v4i32.v4f32(<4 x float> %tmp1)
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ret <4 x i32> %tmp2
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}
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define <2 x i32> @vcvtpsd(<2 x float>* %A) {
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; CHECK: vcvtpsd
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; CHECK: vcvtp.s32.f32 d{{[0-9]+}}, d{{[0-9]+}}
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%tmp1 = load <2 x float>* %A
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%tmp2 = call <2 x i32> @llvm.arm.neon.vcvtps.v2i32.v2f32(<2 x float> %tmp1)
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ret <2 x i32> %tmp2
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}
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define <4 x i32> @vcvtmsq(<4 x float>* %A) {
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; CHECK: vcvtmsq
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; CHECK: vcvtm.s32.f32 q{{[0-9]+}}, q{{[0-9]+}}
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%tmp1 = load <4 x float>* %A
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%tmp2 = call <4 x i32> @llvm.arm.neon.vcvtms.v4i32.v4f32(<4 x float> %tmp1)
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ret <4 x i32> %tmp2
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}
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define <2 x i32> @vcvtmsd(<2 x float>* %A) {
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; CHECK: vcvtmsd
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; CHECK: vcvtm.s32.f32 d{{[0-9]+}}, d{{[0-9]+}}
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%tmp1 = load <2 x float>* %A
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%tmp2 = call <2 x i32> @llvm.arm.neon.vcvtms.v2i32.v2f32(<2 x float> %tmp1)
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ret <2 x i32> %tmp2
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}
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define <4 x i32> @vcvtauq(<4 x float>* %A) {
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; CHECK: vcvtauq
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; CHECK: vcvta.u32.f32 q{{[0-9]+}}, q{{[0-9]+}}
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%tmp1 = load <4 x float>* %A
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%tmp2 = call <4 x i32> @llvm.arm.neon.vcvtau.v4i32.v4f32(<4 x float> %tmp1)
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ret <4 x i32> %tmp2
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}
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define <2 x i32> @vcvtaud(<2 x float>* %A) {
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; CHECK: vcvtaud
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; CHECK: vcvta.u32.f32 d{{[0-9]+}}, d{{[0-9]+}}
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%tmp1 = load <2 x float>* %A
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%tmp2 = call <2 x i32> @llvm.arm.neon.vcvtau.v2i32.v2f32(<2 x float> %tmp1)
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ret <2 x i32> %tmp2
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}
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define <4 x i32> @vcvtnuq(<4 x float>* %A) {
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; CHECK: vcvtnuq
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; CHECK: vcvtn.u32.f32 q{{[0-9]+}}, q{{[0-9]+}}
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%tmp1 = load <4 x float>* %A
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%tmp2 = call <4 x i32> @llvm.arm.neon.vcvtnu.v4i32.v4f32(<4 x float> %tmp1)
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ret <4 x i32> %tmp2
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}
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define <2 x i32> @vcvtnud(<2 x float>* %A) {
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; CHECK: vcvtnud
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; CHECK: vcvtn.u32.f32 d{{[0-9]+}}, d{{[0-9]+}}
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%tmp1 = load <2 x float>* %A
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%tmp2 = call <2 x i32> @llvm.arm.neon.vcvtnu.v2i32.v2f32(<2 x float> %tmp1)
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ret <2 x i32> %tmp2
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}
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define <4 x i32> @vcvtpuq(<4 x float>* %A) {
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; CHECK: vcvtpuq
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; CHECK: vcvtp.u32.f32 q{{[0-9]+}}, q{{[0-9]+}}
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%tmp1 = load <4 x float>* %A
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%tmp2 = call <4 x i32> @llvm.arm.neon.vcvtpu.v4i32.v4f32(<4 x float> %tmp1)
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ret <4 x i32> %tmp2
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}
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define <2 x i32> @vcvtpud(<2 x float>* %A) {
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; CHECK: vcvtpud
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; CHECK: vcvtp.u32.f32 d{{[0-9]+}}, d{{[0-9]+}}
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%tmp1 = load <2 x float>* %A
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%tmp2 = call <2 x i32> @llvm.arm.neon.vcvtpu.v2i32.v2f32(<2 x float> %tmp1)
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ret <2 x i32> %tmp2
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}
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define <4 x i32> @vcvtmuq(<4 x float>* %A) {
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; CHECK: vcvtmuq
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; CHECK: vcvtm.u32.f32 q{{[0-9]+}}, q{{[0-9]+}}
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%tmp1 = load <4 x float>* %A
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%tmp2 = call <4 x i32> @llvm.arm.neon.vcvtmu.v4i32.v4f32(<4 x float> %tmp1)
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ret <4 x i32> %tmp2
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}
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define <2 x i32> @vcvtmud(<2 x float>* %A) {
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; CHECK: vcvtmud
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; CHECK: vcvtm.u32.f32 d{{[0-9]+}}, d{{[0-9]+}}
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%tmp1 = load <2 x float>* %A
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%tmp2 = call <2 x i32> @llvm.arm.neon.vcvtmu.v2i32.v2f32(<2 x float> %tmp1)
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ret <2 x i32> %tmp2
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}
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declare <4 x i32> @llvm.arm.neon.vcvtas.v4i32.v4f32(<4 x float>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vcvtas.v2i32.v2f32(<2 x float>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vcvtns.v4i32.v4f32(<4 x float>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vcvtns.v2i32.v2f32(<2 x float>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vcvtps.v4i32.v4f32(<4 x float>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vcvtps.v2i32.v2f32(<2 x float>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vcvtms.v4i32.v4f32(<4 x float>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vcvtms.v2i32.v2f32(<2 x float>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vcvtau.v4i32.v4f32(<4 x float>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vcvtau.v2i32.v2f32(<2 x float>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vcvtnu.v4i32.v4f32(<4 x float>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vcvtnu.v2i32.v2f32(<2 x float>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vcvtpu.v4i32.v4f32(<4 x float>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vcvtpu.v2i32.v2f32(<2 x float>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vcvtmu.v4i32.v4f32(<4 x float>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vcvtmu.v2i32.v2f32(<2 x float>) nounwind readnone
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