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R600/SI: add VOP mapping functions

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Make it possible to map between e32 and e64 encoding opcodes.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176104 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Christian Konig 2013-02-26 17:52:42 +00:00
parent b37afdcf3f
commit f767018b10
3 changed files with 35 additions and 11 deletions
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1
lib/Target/R600/AMDGPUInstrInfo.cpp
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@ -22,6 +22,7 @@
#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h"
#define GET_INSTRINFO_CTOR #define GET_INSTRINFO_CTOR
#define GET_INSTRMAP_INFO
#include "AMDGPUGenInstrInfo.inc" #include "AMDGPUGenInstrInfo.inc"
using namespace llvm; using namespace llvm;

6
lib/Target/R600/SIInstrInfo.h
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@ -73,6 +73,12 @@ public:
virtual const TargetRegisterClass *getSuperIndirectRegClass() const; virtual const TargetRegisterClass *getSuperIndirectRegClass() const;
}; };
namespace AMDGPU {
int getVOPe64(uint16_t Opcode);
} // End namespace AMDGPU
} // End namespace llvm } // End namespace llvm
namespace SIInstrFlags { namespace SIInstrFlags {

39
lib/Target/R600/SIInstrInfo.td
View File

@ -143,13 +143,17 @@ multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass dstClass> {
// Vector ALU classes // Vector ALU classes
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class VOP <string opName> {
string OpName = opName;
}
multiclass VOP1_Helper <bits<8> op, RegisterClass drc, RegisterClass src, multiclass VOP1_Helper <bits<8> op, RegisterClass drc, RegisterClass src,
string opName, list<dag> pattern> { string opName, list<dag> pattern> {
def _e32: VOP1 < def _e32 : VOP1 <
op, (outs drc:$dst), (ins src:$src0), op, (outs drc:$dst), (ins src:$src0),
opName#"_e32 $dst, $src0", pattern opName#"_e32 $dst, $src0", pattern
>; >, VOP <opName>;
def _e64 : VOP3 < def _e64 : VOP3 <
{1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}}, {1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
@ -158,7 +162,7 @@ multiclass VOP1_Helper <bits<8> op, RegisterClass drc, RegisterClass src,
i32imm:$abs, i32imm:$clamp, i32imm:$abs, i32imm:$clamp,
i32imm:$omod, i32imm:$neg), i32imm:$omod, i32imm:$neg),
opName#"_e64 $dst, $src0, $abs, $clamp, $omod, $neg", [] opName#"_e64 $dst, $src0, $abs, $clamp, $omod, $neg", []
> { >, VOP <opName> {
let SRC1 = SIOperand.ZERO; let SRC1 = SIOperand.ZERO;
let SRC2 = SIOperand.ZERO; let SRC2 = SIOperand.ZERO;
} }
@ -175,7 +179,7 @@ multiclass VOP2_Helper <bits<6> op, RegisterClass vrc, RegisterClass arc,
def _e32 : VOP2 < def _e32 : VOP2 <
op, (outs vrc:$dst), (ins arc:$src0, vrc:$src1), op, (outs vrc:$dst), (ins arc:$src0, vrc:$src1),
opName#"_e32 $dst, $src0, $src1", pattern opName#"_e32 $dst, $src0, $src1", pattern
>; >, VOP <opName>;
def _e64 : VOP3 < def _e64 : VOP3 <
{1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}}, {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
@ -184,7 +188,7 @@ multiclass VOP2_Helper <bits<6> op, RegisterClass vrc, RegisterClass arc,
i32imm:$abs, i32imm:$clamp, i32imm:$abs, i32imm:$clamp,
i32imm:$omod, i32imm:$neg), i32imm:$omod, i32imm:$neg),
opName#"_e64 $dst, $src0, $src1, $abs, $clamp, $omod, $neg", [] opName#"_e64 $dst, $src0, $src1, $abs, $clamp, $omod, $neg", []
> { >, VOP <opName> {
let SRC2 = SIOperand.ZERO; let SRC2 = SIOperand.ZERO;
} }
} }
@ -200,7 +204,7 @@ multiclass VOP2b_32 <bits<6> op, string opName, list<dag> pattern> {
def _e32 : VOP2 < def _e32 : VOP2 <
op, (outs VReg_32:$dst), (ins VSrc_32:$src0, VReg_32:$src1), op, (outs VReg_32:$dst), (ins VSrc_32:$src0, VReg_32:$src1),
opName#"_e32 $dst, $src0, $src1", pattern opName#"_e32 $dst, $src0, $src1", pattern
>; >, VOP <opName>;
def _e64 : VOP3b < def _e64 : VOP3b <
{1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}}, {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
@ -209,7 +213,7 @@ multiclass VOP2b_32 <bits<6> op, string opName, list<dag> pattern> {
i32imm:$abs, i32imm:$clamp, i32imm:$abs, i32imm:$clamp,
i32imm:$omod, i32imm:$neg), i32imm:$omod, i32imm:$neg),
opName#"_e64 $dst, $src0, $src1, $abs, $clamp, $omod, $neg", [] opName#"_e64 $dst, $src0, $src1, $abs, $clamp, $omod, $neg", []
> { >, VOP <opName> {
let SRC2 = SIOperand.ZERO; let SRC2 = SIOperand.ZERO;
/* the VOP2 variant puts the carry out into VCC, the VOP3 variant /* the VOP2 variant puts the carry out into VCC, the VOP3 variant
can write it into any SGPR. We currently don't use the carry out, can write it into any SGPR. We currently don't use the carry out,
@ -224,7 +228,7 @@ multiclass VOPC_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
def _e32 : VOPC < def _e32 : VOPC <
op, (ins arc:$src0, vrc:$src1), op, (ins arc:$src0, vrc:$src1),
opName#"_e32 $dst, $src0, $src1", [] opName#"_e32 $dst, $src0, $src1", []
>; >, VOP <opName>;
def _e64 : VOP3 < def _e64 : VOP3 <
{0, op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}}, {0, op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
@ -236,7 +240,7 @@ multiclass VOPC_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
!if(!eq(!cast<string>(cond), "COND_NULL"), []<dag>, !if(!eq(!cast<string>(cond), "COND_NULL"), []<dag>,
[(set SReg_64:$dst, (i1 (setcc (vt arc:$src0), arc:$src1, cond)))] [(set SReg_64:$dst, (i1 (setcc (vt arc:$src0), arc:$src1, cond)))]
) )
> { >, VOP <opName> {
let SRC2 = SIOperand.ZERO; let SRC2 = SIOperand.ZERO;
} }
} }
@ -254,14 +258,14 @@ class VOP3_32 <bits<9> op, string opName, list<dag> pattern> : VOP3 <
(ins VSrc_32:$src0, VSrc_32:$src1, VSrc_32:$src2, (ins VSrc_32:$src0, VSrc_32:$src1, VSrc_32:$src2,
i32imm:$abs, i32imm:$clamp, i32imm:$omod, i32imm:$neg), i32imm:$abs, i32imm:$clamp, i32imm:$omod, i32imm:$neg),
opName#" $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", pattern opName#" $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", pattern
>; >, VOP <opName>;
class VOP3_64 <bits<9> op, string opName, list<dag> pattern> : VOP3 < class VOP3_64 <bits<9> op, string opName, list<dag> pattern> : VOP3 <
op, (outs VReg_64:$dst), op, (outs VReg_64:$dst),
(ins VSrc_64:$src0, VSrc_64:$src1, VSrc_64:$src2, (ins VSrc_64:$src0, VSrc_64:$src1, VSrc_64:$src2,
i32imm:$abs, i32imm:$clamp, i32imm:$omod, i32imm:$neg), i32imm:$abs, i32imm:$clamp, i32imm:$omod, i32imm:$neg),
opName#" $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", pattern opName#" $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", pattern
>; >, VOP <opName>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Vector I/O classes // Vector I/O classes
@ -319,4 +323,17 @@ class MIMG_Load_Helper <bits<7> op, string asm> : MIMG <
let mayStore = 0; let mayStore = 0;
} }
//===----------------------------------------------------------------------===//
// Vector instruction mappings
//===----------------------------------------------------------------------===//
// Maps an opcode in e32 form to its e64 equivalent
def getVOPe64 : InstrMapping {
let FilterClass = "VOP";
let RowFields = ["OpName"];
let ColFields = ["Size"];
let KeyCol = ["4"];
let ValueCols = [["8"]];
}
include "SIInstructions.td" include "SIInstructions.td"