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https://github.com/c64scene-ar/llvm-6502.git
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Improve MSan tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169256 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evgeniy Stepanov
parent
30cd56bc56
commit
f76bd101fe
@ -21,13 +21,13 @@ if.end: ; preds = %entry, %if.then
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declare void @foo(...)
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; CHECK: define void @LoadAndCmp
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; CHECK: @LoadAndCmp
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; CHECK: = load
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; CHECK: = load
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; CHECK: call void @__msan_warning_noreturn()
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; CHECK-NEXT: call void asm sideeffect
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; CHECK-NEXT: unreachable
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; CHECK: }
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; CHECK: ret void
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; Check that we store the shadow for the retval.
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define i32 @ReturnInt() nounwind uwtable readnone {
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@ -35,9 +35,9 @@ entry:
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ret i32 123
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}
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; CHECK: define i32 @ReturnInt()
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; CHECK: @ReturnInt
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; CHECK: store i32 0,{{.*}}__msan_retval_tls
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; CHECK: }
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; CHECK: ret i32
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; Check that we get the shadow for the retval.
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define void @CopyRetVal(i32* nocapture %a) nounwind uwtable {
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@ -47,11 +47,11 @@ entry:
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ret void
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}
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; CHECK: define void @CopyRetVal
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; CHECK: @CopyRetVal
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; CHECK: load{{.*}}__msan_retval_tls
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; CHECK: store
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; CHECK: store
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; CHECK: }
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; CHECK: ret void
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; Check that we generate PHIs for shadow.
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@ -74,12 +74,12 @@ entry:
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ret void
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}
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; CHECK: define void @FuncWithPhi
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; CHECK: @FuncWithPhi
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; CHECK: = phi
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; CHECK-NEXT: = phi
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; CHECK: store
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; CHECK: store
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; CHECK: }
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; CHECK: ret void
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; Compute shadow for "x << 10"
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define void @ShlConst(i32* nocapture %x) nounwind uwtable {
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@ -90,14 +90,14 @@ entry:
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ret void
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}
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; CHECK: define void @ShlConst
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; CHECK: @ShlConst
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; CHECK: = load
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; CHECK: = load
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; CHECK: shl
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; CHECK: shl
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; CHECK: store
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; CHECK: store
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; CHECK: }
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; CHECK: ret void
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; Compute shadow for "10 << x": it should have 'sext i1'.
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define void @ShlNonConst(i32* nocapture %x) nounwind uwtable {
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@ -108,13 +108,13 @@ entry:
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ret void
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}
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; CHECK: define void @ShlNonConst
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; CHECK: @ShlNonConst
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; CHECK: = load
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; CHECK: = load
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; CHECK: = sext i1
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; CHECK: store
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; CHECK: store
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; CHECK: }
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; CHECK: ret void
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; SExt
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define void @SExt(i32* nocapture %a, i16* nocapture %b) nounwind uwtable {
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@ -125,14 +125,14 @@ entry:
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ret void
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}
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; CHECK: define void @SExt
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; CHECK: @SExt
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; CHECK: = load
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; CHECK: = load
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; CHECK: = sext
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; CHECK: = sext
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; CHECK: store
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; CHECK: store
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; CHECK: }
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; CHECK: ret void
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; memset
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@ -144,9 +144,9 @@ entry:
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declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind
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; CHECK: define void @MemSet
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; CHECK: @MemSet
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; CHECK: call i8* @__msan_memset
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; CHECK: }
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; CHECK: ret void
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; memcpy
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@ -158,9 +158,9 @@ entry:
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declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind
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; CHECK: define void @MemCpy
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; CHECK: @MemCpy
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; CHECK: call i8* @__msan_memcpy
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; CHECK: }
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; CHECK: ret void
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; memmove is lowered to a call
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@ -172,9 +172,9 @@ entry:
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declare void @llvm.memmove.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind
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; CHECK: define void @MemMove
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; CHECK: @MemMove
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; CHECK: call i8* @__msan_memmove
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; CHECK: }
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; CHECK: ret void
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; Check that we propagate shadow for "select"
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@ -186,10 +186,10 @@ entry:
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ret i32 %cond
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}
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; CHECK: define i32 @Select
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; CHECK: @Select
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; CHECK: select
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; CHECK-NEXT: select
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; CHECK: }
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; CHECK: ret i32
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define i8* @IntToPtr(i64 %x) nounwind uwtable readnone {
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@ -198,11 +198,11 @@ entry:
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ret i8* %0
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}
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; CHECK: define i8* @IntToPtr
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; CHECK: @IntToPtr
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; CHECK: load i64*{{.*}}__msan_param_tls
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; CHECK-NEXT: inttoptr
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; CHECK-NEXT: store i64{{.*}}__msan_retval_tls
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; CHECK: }
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; CHECK: ret i8
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define i8* @IntToPtr_ZExt(i16 %x) nounwind uwtable readnone {
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@ -211,10 +211,10 @@ entry:
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ret i8* %0
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}
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; CHECK: define i8* @IntToPtr_ZExt
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; CHECK: @IntToPtr_ZExt
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; CHECK: zext
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; CHECK-NEXT: inttoptr
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; CHECK: }
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; CHECK: ret i8
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; Check that we insert exactly one check on udiv
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@ -226,13 +226,13 @@ entry:
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ret i32 %div
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}
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; CHECK: define i32 @Div
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; CHECK: @Div
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; CHECK: icmp
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; CHECK: br
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; CHECK: call void @__msan_warning
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; CHECK-NOT: icmp
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; CHECK: udiv
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; CHECK-NOT: icmp
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; CHECK: }
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; CHECK: ret i32
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; Check that we propagate shadow for x<0, x>=0, etc (i.e. sign bit tests)
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@ -242,44 +242,48 @@ define zeroext i1 @ICmpSLT(i32 %x) nounwind uwtable readnone {
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ret i1 %1
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}
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; CHECK: define zeroext i1 @ICmpSLT
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; CHECK: @ICmpSLT
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; CHECK: icmp slt
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; CHECK-NOT: call void @__msan_warning
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; CHECK: icmp slt
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; CHECK-NOT: br
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; CHECK: }
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; CHECK-NOT: call void @__msan_warning
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; CHECK: ret i1
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define zeroext i1 @ICmpSGE(i32 %x) nounwind uwtable readnone {
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%1 = icmp sge i32 %x, 0
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ret i1 %1
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}
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; CHECK: define zeroext i1 @ICmpSGE
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; CHECK: @ICmpSGE
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; CHECK: icmp slt
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; CHECK-NOT: call void @__msan_warning
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; CHECK: icmp sge
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; CHECK-NOT: br
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; CHECK: }
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; CHECK-NOT: call void @__msan_warning
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; CHECK: ret i1
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define zeroext i1 @ICmpSGT(i32 %x) nounwind uwtable readnone {
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%1 = icmp sgt i32 0, %x
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ret i1 %1
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}
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; CHECK: define zeroext i1 @ICmpSGT
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; CHECK: @ICmpSGT
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; CHECK: icmp slt
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; CHECK-NOT: call void @__msan_warning
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; CHECK: icmp sgt
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; CHECK-NOT: br
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; CHECK: }
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; CHECK-NOT: call void @__msan_warning
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; CHECK: ret i1
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define zeroext i1 @ICmpSLE(i32 %x) nounwind uwtable readnone {
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%1 = icmp sle i32 0, %x
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ret i1 %1
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}
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; CHECK: define zeroext i1 @ICmpSLE
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; CHECK: @ICmpSLE
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; CHECK: icmp slt
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; CHECK-NOT: call void @__msan_warning
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; CHECK: icmp sle
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; CHECK-NOT: br
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; CHECK: }
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; CHECK-NOT: call void @__msan_warning
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; CHECK: ret i1
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; Check that loads from shadow have the same aligment as the original loads.
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@ -290,10 +294,10 @@ define i32 @ShadowLoadAlignmentLarge() nounwind uwtable {
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ret i32 %1
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}
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; CHECK: define i32 @ShadowLoadAlignmentLarge
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; CHECK: @ShadowLoadAlignmentLarge
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; CHECK: load i32* {{.*}} align 64
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; CHECK: load volatile i32* {{.*}} align 64
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; CHECK: }
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; CHECK: ret i32
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define i32 @ShadowLoadAlignmentSmall() nounwind uwtable {
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%y = alloca i32, align 2
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@ -301,35 +305,37 @@ define i32 @ShadowLoadAlignmentSmall() nounwind uwtable {
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ret i32 %1
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}
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; CHECK: define i32 @ShadowLoadAlignmentSmall
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; CHECK: @ShadowLoadAlignmentSmall
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; CHECK: load i32* {{.*}} align 2
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; CHECK: load volatile i32* {{.*}} align 2
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; CHECK: }
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; CHECK: ret i32
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; Test vector manipulation instructions.
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; Check that the same bit manipulation is applied to the shadow values.
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; Check that there is a zero test of the shadow of %idx argument, where present.
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define i32 @ExtractElement(<4 x i32> %vec, i32 %idx) {
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%x = extractelement <4 x i32> %vec, i32 %idx
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ret i32 %x
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}
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; CHECK: define i32 @ExtractElement
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; CHECK: @ExtractElement
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; CHECK: extractelement
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; CHECK: br
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; CHECK: call void @__msan_warning
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; CHECK: extractelement
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; CHECK: }
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; CHECK: ret i32
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define <4 x i32> @InsertElement(<4 x i32> %vec, i32 %idx, i32 %x) {
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%vec1 = insertelement <4 x i32> %vec, i32 %x, i32 %idx
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ret <4 x i32> %vec1
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}
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; CHECK: define <4 x i32> @InsertElement
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; CHECK: @InsertElement
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; CHECK: insertelement
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; CHECK: br
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; CHECK: call void @__msan_warning
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; CHECK: insertelement
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; CHECK: }
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; CHECK: ret <4 x i32>
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define <4 x i32> @ShuffleVector(<4 x i32> %vec, <4 x i32> %vec1) {
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%vec2 = shufflevector <4 x i32> %vec, <4 x i32> %vec1,
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@ -337,8 +343,8 @@ define <4 x i32> @ShuffleVector(<4 x i32> %vec, <4 x i32> %vec1) {
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ret <4 x i32> %vec2
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}
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; CHECK: define <4 x i32> @ShuffleVector
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; CHECK: @ShuffleVector
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; CHECK: shufflevector
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; CHECK-NOT: br
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; CHECK-NOT: call void @__msan_warning
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; CHECK: shufflevector
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; CHECK: }
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; CHECK: ret <4 x i32>
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