6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-26 05:32:25 +00:00
Code Issues Projects Releases Wiki Activity

[mips][mips64r6] Add relocations R_MIPS_PC21_S2, R_MIPS_PC26_S2

Browse Source 
Differential Revision: http://reviews.llvm.org/D3824


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209655 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Zoran Jovanovic 2014-05-27 12:55:40 +00:00
parent 18b6fb9612
commit f7744906f0
6 changed files with 124 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
View File

@ -102,6 +102,22 @@ static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
if (!isIntN(16, Value) && Ctx) if (!isIntN(16, Value) && Ctx)
Ctx->FatalError(Fixup.getLoc(), "out of range PC16 fixup"); Ctx->FatalError(Fixup.getLoc(), "out of range PC16 fixup");
break; break;
case Mips::fixup_MIPS_PC21_S2:
Value -= 4;
// Forcing a signed division because Value can be negative.
Value = (int64_t) Value / 4;
// We now check if Value can be encoded as a 21-bit signed immediate.
if (!isIntN(21, Value) && Ctx)
Ctx->FatalError(Fixup.getLoc(), "out of range PC21 fixup");
break;
case Mips::fixup_MIPS_PC26_S2:
Value -= 4;
// Forcing a signed division because Value can be negative.
Value = (int64_t) Value / 4;
// We now check if Value can be encoded as a 26-bit signed immediate.
if (!isIntN(26, Value) && Ctx)
Ctx->FatalError(Fixup.getLoc(), "out of range PC26 fixup");
break;
} }
return Value; return Value;
@ -229,6 +245,8 @@ getFixupKindInfo(MCFixupKind Kind) const {
{ "fixup_Mips_GOT_LO16", 0, 16, 0 }, { "fixup_Mips_GOT_LO16", 0, 16, 0 },
{ "fixup_Mips_CALL_HI16", 0, 16, 0 }, { "fixup_Mips_CALL_HI16", 0, 16, 0 },
{ "fixup_Mips_CALL_LO16", 0, 16, 0 }, { "fixup_Mips_CALL_LO16", 0, 16, 0 },
{ "fixup_MIPS_PC21_S2", 0, 21, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MIPS_PC26_S2", 0, 26, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MICROMIPS_26_S1", 0, 26, 0 }, { "fixup_MICROMIPS_26_S1", 0, 26, 0 },
{ "fixup_MICROMIPS_HI16", 0, 16, 0 }, { "fixup_MICROMIPS_HI16", 0, 16, 0 },
{ "fixup_MICROMIPS_LO16", 0, 16, 0 }, { "fixup_MICROMIPS_LO16", 0, 16, 0 },
@ -286,6 +304,8 @@ getFixupKindInfo(MCFixupKind Kind) const {
{ "fixup_Mips_GOT_LO16", 16, 16, 0 }, { "fixup_Mips_GOT_LO16", 16, 16, 0 },
{ "fixup_Mips_CALL_HI16", 16, 16, 0 }, { "fixup_Mips_CALL_HI16", 16, 16, 0 },
{ "fixup_Mips_CALL_LO16", 16, 16, 0 }, { "fixup_Mips_CALL_LO16", 16, 16, 0 },
{ "fixup_MIPS_PC21_S2", 11, 21, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MIPS_PC26_S2", 6, 26, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MICROMIPS_26_S1", 6, 26, 0 }, { "fixup_MICROMIPS_26_S1", 6, 26, 0 },
{ "fixup_MICROMIPS_HI16", 16, 16, 0 }, { "fixup_MICROMIPS_HI16", 16, 16, 0 },
{ "fixup_MICROMIPS_LO16", 16, 16, 0 }, { "fixup_MICROMIPS_LO16", 16, 16, 0 },

6
lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
View File

@ -193,6 +193,12 @@ unsigned MipsELFObjectWriter::GetRelocType(const MCValue &Target,
case Mips::fixup_MICROMIPS_TLS_TPREL_LO16: case Mips::fixup_MICROMIPS_TLS_TPREL_LO16:
Type = ELF::R_MICROMIPS_TLS_TPREL_LO16; Type = ELF::R_MICROMIPS_TLS_TPREL_LO16;
break; break;
case Mips::fixup_MIPS_PC21_S2:
Type = ELF::R_MIPS_PC21_S2;
break;
case Mips::fixup_MIPS_PC26_S2:
Type = ELF::R_MIPS_PC26_S2;
break;
} }
return Type; return Type;
} }

6
lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h
View File

@ -128,6 +128,12 @@ namespace Mips {
// resulting in - R_MIPS_CALL_LO16 // resulting in - R_MIPS_CALL_LO16
fixup_Mips_CALL_LO16, fixup_Mips_CALL_LO16,
// resulting in - R_MIPS_PC21_S2
fixup_MIPS_PC21_S2,
// resulting in - R_MIPS_PC26_S2
fixup_MIPS_PC26_S2,
// resulting in - R_MICROMIPS_26_S1 // resulting in - R_MICROMIPS_26_S1
fixup_MICROMIPS_26_S1, fixup_MICROMIPS_26_S1,

8
lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
View File

@ -258,7 +258,9 @@ getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo,
assert(MO.isExpr() && assert(MO.isExpr() &&
"getBranchTarget21OpValue expects only expressions or immediates"); "getBranchTarget21OpValue expects only expressions or immediates");
// TODO: Push 21 PC fixup. const MCExpr *Expr = MO.getExpr();
Fixups.push_back(MCFixup::Create(0, Expr,
MCFixupKind(Mips::fixup_MIPS_PC21_S2)));
return 0; return 0;
} }
@ -278,7 +280,9 @@ getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo,
assert(MO.isExpr() && assert(MO.isExpr() &&
"getBranchTarget26OpValue expects only expressions or immediates"); "getBranchTarget26OpValue expects only expressions or immediates");
// TODO: Push 26 PC fixup. const MCExpr *Expr = MO.getExpr();
Fixups.push_back(MCFixup::Create(0, Expr,
MCFixupKind(Mips::fixup_MIPS_PC26_S2)));
return 0; return 0;
} }

43
test/MC/Mips/mips32r6/relocations.s Normal file
View File

@ -0,0 +1,43 @@
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \
# RUN: | FileCheck %s -check-prefix=CHECK-FIXUP
# RUN: llvm-mc %s -filetype=obj -triple=mips-unknown-linux -mcpu=mips32r6 \
# RUN: | llvm-readobj -r | FileCheck %s -check-prefix=CHECK-ELF
#------------------------------------------------------------------------------
# Check that the assembler can handle the documented syntax for fixups.
#------------------------------------------------------------------------------
# CHECK-FIXUP: beqc $5, $6, bar # encoding: [0x20,0xa6,A,A]
# CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_Mips_PC16
# CHECK-FIXUP: bnec $5, $6, bar # encoding: [0x60,0xa6,A,A]
# CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_Mips_PC16
# CHECK-FIXUP: beqzc $9, bar # encoding: [0xd9,0b001AAAAA,A,A]
# CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC21_S2
# CHECK-FIXUP: bnezc $9, bar # encoding: [0xf9,0b001AAAAA,A,A]
# CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC21_S2
# CHECK-FIXUP: balc bar # encoding: [0b111010AA,A,A,A]
# CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC26_S2
# CHECK-FIXUP: bc bar # encoding: [0b110010AA,A,A,A]
# CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC26_S2
#------------------------------------------------------------------------------
# Check that the appropriate relocations were created.
#------------------------------------------------------------------------------
# CHECK-ELF: Relocations [
# CHECK-ELF: 0x0 R_MIPS_PC16 bar 0x0
# CHECK-ELF: 0x4 R_MIPS_PC16 bar 0x0
# CHECK-ELF: 0x8 R_MIPS_PC21_S2 bar 0x0
# CHECK-ELF: 0xC R_MIPS_PC21_S2 bar 0x0
# CHECK-ELF: 0x10 R_MIPS_PC26_S2 bar 0x0
# CHECK-ELF: 0x14 R_MIPS_PC26_S2 bar 0x0
# CHECK-ELF: ]
beqc $5, $6, bar
bnec $5, $6, bar
beqzc $9, bar
bnezc $9, bar
balc bar
bc bar

43
test/MC/Mips/mips64r6/relocations.s Normal file
View File

@ -0,0 +1,43 @@
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r6 \
# RUN: | FileCheck %s -check-prefix=CHECK-FIXUP
# RUN: llvm-mc %s -filetype=obj -triple=mips-unknown-linux -mcpu=mips64r6 \
# RUN: | llvm-readobj -r | FileCheck %s -check-prefix=CHECK-ELF
#------------------------------------------------------------------------------
# Check that the assembler can handle the documented syntax for fixups.
#------------------------------------------------------------------------------
# CHECK-FIXUP: beqc $5, $6, bar # encoding: [0x20,0xa6,A,A]
# CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_Mips_PC16
# CHECK-FIXUP: bnec $5, $6, bar # encoding: [0x60,0xa6,A,A]
# CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_Mips_PC16
# CHECK-FIXUP: beqzc $9, bar # encoding: [0xd9,0b001AAAAA,A,A]
# CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC21_S2
# CHECK-FIXUP: bnezc $9, bar # encoding: [0xf9,0b001AAAAA,A,A]
# CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC21_S2
# CHECK-FIXUP: balc bar # encoding: [0b111010AA,A,A,A]
# CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC26_S2
# CHECK-FIXUP: bc bar # encoding: [0b110010AA,A,A,A]
# CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC26_S2
#------------------------------------------------------------------------------
# Check that the appropriate relocations were created.
#------------------------------------------------------------------------------
# CHECK-ELF: Relocations [
# CHECK-ELF: 0x0 R_MIPS_PC16 bar 0x0
# CHECK-ELF: 0x4 R_MIPS_PC16 bar 0x0
# CHECK-ELF: 0x8 R_MIPS_PC21_S2 bar 0x0
# CHECK-ELF: 0xC R_MIPS_PC21_S2 bar 0x0
# CHECK-ELF: 0x10 R_MIPS_PC26_S2 bar 0x0
# CHECK-ELF: 0x14 R_MIPS_PC26_S2 bar 0x0
# CHECK-ELF: ]
beqc $5, $6, bar
bnec $5, $6, bar
beqzc $9, bar
bnezc $9, bar
balc bar
bc bar