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fix copy/paste errors, and add imm support to SxADDQ and SxSUBQ

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21121 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth 2005-04-06 20:59:59 +00:00
parent 6d027f2e6f
commit f77f395043
1 changed files with 32 additions and 8 deletions
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40
lib/Target/Alpha/AlphaISelPattern.cpp
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@ -1703,34 +1703,58 @@ unsigned ISel::SelectExpr(SDOperand N) {
N.getOperand(0).getOperand(1).getOpcode() == ISD::Constant &&
cast<ConstantSDNode>(N.getOperand(0).getOperand(1))->getValue() == 2)
{
Tmp1 = SelectExpr(N.getOperand(1));
Tmp2 = SelectExpr(N.getOperand(0).getOperand(0));
BuildMI(BB, isAdd?Alpha::S4ADDQ:Alpha::S4SUBQ, 2, Result).addReg(Tmp2).addReg(Tmp1);
if (N.getOperand(1).getOpcode() == ISD::Constant &&
cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 255)
BuildMI(BB, isAdd?Alpha::S4ADDQi:Alpha::S4SUBQi, 2, Result).addReg(Tmp2)
.addImm(cast<ConstantSDNode>(N.getOperand(1))->getValue());
else {
Tmp1 = SelectExpr(N.getOperand(1));
BuildMI(BB, isAdd?Alpha::S4ADDQ:Alpha::S4SUBQ, 2, Result).addReg(Tmp2).addReg(Tmp1);
}
}
else if(N.getOperand(0).getOpcode() == ISD::SHL &&
N.getOperand(0).getOperand(1).getOpcode() == ISD::Constant &&
cast<ConstantSDNode>(N.getOperand(0).getOperand(1))->getValue() == 3)
{
Tmp1 = SelectExpr(N.getOperand(1));
Tmp2 = SelectExpr(N.getOperand(0).getOperand(0));
BuildMI(BB, isAdd?Alpha::S4ADDQ:Alpha::S8SUBQ, 2, Result).addReg(Tmp2).addReg(Tmp1);
if (N.getOperand(1).getOpcode() == ISD::Constant &&
cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 255)
BuildMI(BB, isAdd?Alpha::S8ADDQi:Alpha::S8SUBQi, 2, Result).addReg(Tmp2)
.addImm(cast<ConstantSDNode>(N.getOperand(1))->getValue());
else {
Tmp1 = SelectExpr(N.getOperand(1));
BuildMI(BB, isAdd?Alpha::S8ADDQ:Alpha::S8SUBQ, 2, Result).addReg(Tmp2).addReg(Tmp1);
}
}
//Position prevents subs
else if(N.getOperand(1).getOpcode() == ISD::SHL && isAdd &
N.getOperand(1).getOperand(1).getOpcode() == ISD::Constant &&
cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue() == 2)
{
Tmp1 = SelectExpr(N.getOperand(0));
Tmp2 = SelectExpr(N.getOperand(1).getOperand(0));
BuildMI(BB, Alpha::S8ADDQ, 2, Result).addReg(Tmp2).addReg(Tmp1);
if (N.getOperand(0).getOpcode() == ISD::Constant &&
cast<ConstantSDNode>(N.getOperand(0))->getValue() <= 255)
BuildMI(BB, Alpha::S4ADDQi, 2, Result).addReg(Tmp2)
.addImm(cast<ConstantSDNode>(N.getOperand(0))->getValue());
else {
Tmp1 = SelectExpr(N.getOperand(0));
BuildMI(BB, Alpha::S4ADDQ, 2, Result).addReg(Tmp2).addReg(Tmp1);
}
}
else if(N.getOperand(0).getOpcode() == ISD::SHL && isAdd &&
N.getOperand(1).getOperand(1).getOpcode() == ISD::Constant &&
cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue() == 3)
{
Tmp1 = SelectExpr(N.getOperand(0));
Tmp2 = SelectExpr(N.getOperand(1).getOperand(0));
BuildMI(BB, Alpha::S8ADDQ, 2, Result).addReg(Tmp2).addReg(Tmp1);
if (N.getOperand(0).getOpcode() == ISD::Constant &&
cast<ConstantSDNode>(N.getOperand(0))->getValue() <= 255)
BuildMI(BB, Alpha::S8ADDQi, 2, Result).addReg(Tmp2)
.addImm(cast<ConstantSDNode>(N.getOperand(0))->getValue());
else {
Tmp1 = SelectExpr(N.getOperand(0));
BuildMI(BB, Alpha::S8ADDQ, 2, Result).addReg(Tmp2).addReg(Tmp1);
}
}
//small addi
else if(N.getOperand(1).getOpcode() == ISD::Constant &&