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[ARM64] SCVTF and FCVTZS/U are undefined if scale<5> == 0.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205882 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bradley Smith
2014-04-09 14:43:35 +00:00
parent 5c73bde178
commit f797751ca0
3 changed files with 29 additions and 8 deletions
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24
lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
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@@ -82,9 +82,12 @@ static DecodeStatus DecodeDDDDRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeFixedPointScaleImm(llvm::MCInst &Inst, unsigned Imm,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeFixedPointScaleImm32(llvm::MCInst &Inst, unsigned Imm,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeFixedPointScaleImm64(llvm::MCInst &Inst, unsigned Imm,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeCondBranchTarget(llvm::MCInst &Inst, unsigned Imm,
uint64_t Address,
const void *Decoder);
@@ -744,9 +747,18 @@ static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
return Success;
}
static DecodeStatus DecodeFixedPointScaleImm(llvm::MCInst &Inst, unsigned Imm,
uint64_t Addr,
const void *Decoder) {
static DecodeStatus DecodeFixedPointScaleImm32(llvm::MCInst &Inst, unsigned Imm,
uint64_t Addr,
const void *Decoder) {
// scale{5} is asserted as 1 in tblgen.
Imm |= 0x20;
Inst.addOperand(MCOperand::CreateImm(64 - Imm));
return Success;
}
static DecodeStatus DecodeFixedPointScaleImm64(llvm::MCInst &Inst, unsigned Imm,
uint64_t Addr,
const void *Decoder) {
Inst.addOperand(MCOperand::CreateImm(64 - Imm));
return Success;
}