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Clarify intent.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174068 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2013-01-31 17:56:23 +00:00
parent b11917c1aa
commit f79c5e2f84
1 changed files with 6 additions and 0 deletions
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6
utils/TableGen/CodeGenRegisters.cpp
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@ -1198,6 +1198,12 @@ void CodeGenRegBank::computeSubRegIndexLaneMasks() {
if (Idx->getComposites().empty()) {
Idx->LaneMask = 1u << Bit;
// Share bit 31 in the unlikely case there are more than 32 leafs.
//
// Sharing bits is harmless; it allows graceful degradation in targets
// with more than 32 vector lanes. They simply get a limited resolution
// view of lanes beyond the 32nd.
//
// See also the comment for getSubRegIndexLaneMask().
if (Bit < 31) ++Bit;
} else {
Idx->LaneMask = 0;