6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-05-22 03:39:03 +00:00
Code Issues Projects Releases Wiki Activity

Fix interference caused by fmul 2, x -> fadd x, x

Browse Source 
If an fmul was introduced by lowering, it wouldn't be folded
into a multiply by a constant since the earlier combine would
have replaced the fmul with the fadd.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216932 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2014-09-02 19:02:53 +00:00
parent 9bf0327ea7
commit f7a3c7e705
3 changed files with 113 additions and 44 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

29
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -6870,6 +6870,27 @@ SDValue DAGCombiner::visitFMUL(SDNode *N) {
if (N1CFP && N1CFP->isExactlyValue(1.0)) if (N1CFP && N1CFP->isExactlyValue(1.0))
return N0; return N0;
if (DAG.getTarget().Options.UnsafeFPMath) {
// If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
if (N1CFP && N0.getOpcode() == ISD::FMUL &&
N0.getNode()->hasOneUse() && isConstOrConstSplatFP(N0.getOperand(1))) {
SDLoc SL(N);
SDValue MulConsts = DAG.getNode(ISD::FMUL, SL, VT, N0.getOperand(1), N1);
return DAG.getNode(ISD::FMUL, SL, VT, N0.getOperand(0), MulConsts);
}
// If allowed, fold (fmul (fadd x, x), c) -> (fmul x, (fmul 2.0, c))
// Undo the fmul 2.0, x -> fadd x, x transformation, since if it occurs
// during an early run of DAGCombiner can prevent folding with fmuls
// inserted during lowering.
if (N0.getOpcode() == ISD::FADD && N0.getOperand(0) == N0.getOperand(1)) {
SDLoc SL(N);
const SDValue Two = DAG.getConstantFP(2.0, VT);
SDValue MulConsts = DAG.getNode(ISD::FMUL, SL, VT, Two, N1);
return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0.getOperand(0), MulConsts);
}
}
// fold (fmul X, 2.0) -> (fadd X, X) // fold (fmul X, 2.0) -> (fadd X, X)
if (N1CFP && N1CFP->isExactlyValue(+2.0)) if (N1CFP && N1CFP->isExactlyValue(+2.0))
return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0, N0); return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0, N0);
@ -6890,14 +6911,6 @@ SDValue DAGCombiner::visitFMUL(SDNode *N) {
} }
} }
// If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
if (Options.UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
N0.getNode()->hasOneUse() && isConstOrConstSplatFP(N0.getOperand(1))) {
return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0.getOperand(0),
DAG.getNode(ISD::FMUL, SDLoc(N), VT,
N0.getOperand(1), N1));
}
return SDValue(); return SDValue();
} }

25
test/CodeGen/R600/fmul.ll
View File

@ -48,3 +48,28 @@ define void @fmul_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)
store <4 x float> %result, <4 x float> addrspace(1)* %out store <4 x float> %result, <4 x float> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: @test_mul_2_k
; SI: V_MUL_F32
; SI-NOT: V_MUL_F32
; SI: S_ENDPGM
define void @test_mul_2_k(float addrspace(1)* %out, float %x) #0 {
%y = fmul float %x, 2.0
%z = fmul float %y, 3.0
store float %z, float addrspace(1)* %out
ret void
}
; FUNC-LABEL: @test_mul_2_k_inv
; SI: V_MUL_F32
; SI-NOT: V_MUL_F32
; SI-NOT: V_MAD_F32
; SI: S_ENDPGM
define void @test_mul_2_k_inv(float addrspace(1)* %out, float %x) #0 {
%y = fmul float %x, 3.0
%z = fmul float %y, 2.0
store float %z, float addrspace(1)* %out
ret void
}
attributes #0 = { "less-precise-fpmad"="true" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "unsafe-fp-math"="true" }

103
test/CodeGen/R600/llvm.sin.ll
View File

@ -1,53 +1,84 @@
;RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
;RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=SI-SAFE -check-prefix=FUNC %s ; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=SI-SAFE -check-prefix=FUNC %s
;RUN: llc -march=r600 -mcpu=SI -enable-unsafe-fp-math < %s | FileCheck -check-prefix=SI -check-prefix=SI-UNSAFE -check-prefix=FUNC %s ; RUN: llc -march=r600 -mcpu=SI -enable-unsafe-fp-math < %s | FileCheck -check-prefix=SI -check-prefix=SI-UNSAFE -check-prefix=FUNC %s
;FUNC-LABEL: test ; FUNC-LABEL: sin_f32
;EG: MULADD_IEEE * ; EG: MULADD_IEEE *
;EG: FRACT * ; EG: FRACT *
;EG: ADD * ; EG: ADD *
;EG: SIN * T{{[0-9]+\.[XYZW], PV\.[XYZW]}} ; EG: SIN * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
;EG-NOT: SIN ; EG-NOT: SIN
;SI: V_MUL_F32 ; SI: V_MUL_F32
;SI: V_FRACT_F32 ; SI: V_FRACT_F32
;SI: V_SIN_F32 ; SI: V_SIN_F32
;SI-NOT: V_SIN_F32 ; SI-NOT: V_SIN_F32
define void @test(float addrspace(1)* %out, float %x) #1 { define void @sin_f32(float addrspace(1)* %out, float %x) #1 {
%sin = call float @llvm.sin.f32(float %x) %sin = call float @llvm.sin.f32(float %x)
store float %sin, float addrspace(1)* %out store float %sin, float addrspace(1)* %out
ret void ret void
} }
;FUNC-LABEL: testf ; FUNC-LABEL: @sin_3x_f32
;SI-UNSAFE: 4.774 ; SI-UNSAFE-NOT: V_ADD_F32
;SI-UNSAFE: V_MUL_F32 ; SI-UNSAFE: 4.774648e-01
;SI-SAFE: V_MUL_F32 ; SI-UNSAFE: V_MUL_F32
;SI-SAFE: V_MUL_F32 ; SI-SAFE: V_MUL_F32
;SI: V_FRACT_F32 ; SI-SAFE: V_MUL_F32
;SI: V_SIN_F32 ; SI: V_FRACT_F32
;SI-NOT: V_SIN_F32 ; SI: V_SIN_F32
; SI-NOT: V_SIN_F32
define void @sin_3x_f32(float addrspace(1)* %out, float %x) #1 {
%y = fmul float 3.0, %x
%sin = call float @llvm.sin.f32(float %y)
store float %sin, float addrspace(1)* %out
ret void
}
define void @testf(float addrspace(1)* %out, float %x) #1 { ; FUNC-LABEL: @sin_2x_f32
%y = fmul float 3.0, %x ; SI-UNSAFE-NOT: V_ADD_F32
; SI-UNSAFE: 3.183099e-01
; SI-UNSAFE: V_MUL_F32
; SI-SAFE: V_ADD_F32
; SI-SAFE: V_MUL_F32
; SI: V_FRACT_F32
; SI: V_SIN_F32
; SI-NOT: V_SIN_F32
define void @sin_2x_f32(float addrspace(1)* %out, float %x) #1 {
%y = fmul float 2.0, %x
%sin = call float @llvm.sin.f32(float %y)
store float %sin, float addrspace(1)* %out
ret void
}
; FUNC-LABEL: @test_2sin_f32
; SI-UNSAFE: 3.183099e-01
; SI-UNSAFE: V_MUL_F32
; SI-SAFE: V_ADD_F32
; SI-SAFE: V_MUL_F32
; SI: V_FRACT_F32
; SI: V_SIN_F32
; SI-NOT: V_SIN_F32
define void @test_2sin_f32(float addrspace(1)* %out, float %x) #1 {
%y = fmul float 2.0, %x
%sin = call float @llvm.sin.f32(float %y) %sin = call float @llvm.sin.f32(float %y)
store float %sin, float addrspace(1)* %out store float %sin, float addrspace(1)* %out
ret void ret void
} }
;FUNC-LABEL: testv ; FUNC-LABEL: @sin_v4f32
;EG: SIN * T{{[0-9]+\.[XYZW], PV\.[XYZW]}} ; EG: SIN * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
;EG: SIN * T{{[0-9]+\.[XYZW], PV\.[XYZW]}} ; EG: SIN * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
;EG: SIN * T{{[0-9]+\.[XYZW], PV\.[XYZW]}} ; EG: SIN * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
;EG: SIN * T{{[0-9]+\.[XYZW], PV\.[XYZW]}} ; EG: SIN * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
;EG-NOT: SIN ; EG-NOT: SIN
;SI: V_SIN_F32 ; SI: V_SIN_F32
;SI: V_SIN_F32 ; SI: V_SIN_F32
;SI: V_SIN_F32 ; SI: V_SIN_F32
;SI: V_SIN_F32 ; SI: V_SIN_F32
;SI-NOT: V_SIN_F32 ; SI-NOT: V_SIN_F32
define void @testv(<4 x float> addrspace(1)* %out, <4 x float> %vx) #1 { define void @sin_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %vx) #1 {
%sin = call <4 x float> @llvm.sin.v4f32( <4 x float> %vx) %sin = call <4 x float> @llvm.sin.v4f32( <4 x float> %vx)
store <4 x float> %sin, <4 x float> addrspace(1)* %out store <4 x float> %sin, <4 x float> addrspace(1)* %out
ret void ret void