From f7c84bf9ed78c4caeed23cb006ed842eaf5828e1 Mon Sep 17 00:00:00 2001 From: Reed Kotler Date: Fri, 25 Apr 2014 18:05:00 +0000 Subject: [PATCH] Make sure that DSUB does not duplicate the pattern of DSUBU Test Plan: Run test suite to make sure there is no regression. https://dmz-portal.mips.com/bb/builders/LLVM%20with%2064bit%20and%20delay%20slot%20optimizer%20and%20direct%20object%20emitter/builds/626 Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3497 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207247 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/Mips64InstrInfo.td | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index e345aa63dfa..81f805ae63a 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -86,7 +86,7 @@ def DADDu : ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>, ADD_FM<0, 0x2d>; def DSUBu : ArithLogicR<"dsubu", GPR64Opnd, 0, II_DSUBU, sub>, ADD_FM<0, 0x2f>; -def DSUB : ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB, sub>, ADD_FM<0, 0x2e>; +def DSUB : ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB>, ADD_FM<0, 0x2e>; let isCodeGenOnly = 1 in { def SLT64 : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>;