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Instruction definition cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54212 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes
parent
e9a393be13
commit
f7d66f7345
@ -100,11 +100,6 @@ def immZExt16 : PatLeaf<(imm), [{
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return (uint64_t)N->getValue() == (unsigned short)N->getValue();
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}], LO16>;
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// Node immediate fits as 32-bit zero extended on target immediate.
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//def immZExt32 : PatLeaf<(imm), [{
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// return (uint64_t)N->getValue() == (uint32_t)N->getValue();
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//}], LO16>;
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// shamt field must fit in 5 bits.
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def immZExt5 : PatLeaf<(imm), [{
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return N->getValue() == ((N->getValue()) & 0x1f) ;
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@ -398,29 +393,29 @@ def Select_CC : PseudoSelCC<CPURegs, "# MipsSelect_CC_i32">;
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// MipsI Instructions
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//===----------------------------------------------------------------------===//
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// Arithmetic
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// ADDiu just accept 16-bit immediates but we handle this on Pat's.
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// immZExt32 is used here so it can match GlobalAddress immediates.
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// MUL is a assembly macro in the current used ISAs.
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/// Arithmetic Instructions (ALU Immediate)
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def ADDiu : ArithI<0x09, "addiu", add, uimm16, immZExt16>;
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def ADDi : ArithI<0x08, "addi", add, simm16, immSExt16>;
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//def MUL : ArithR<0x1c, 0x02, "mul", mul, IIImul>;
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def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16>;
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def SLTiu : SetCC_I<0x0b, "sltiu", setult, uimm16, immZExt16>;
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def ANDi : LogicI<0x0c, "andi", and>;
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def ORi : LogicI<0x0d, "ori", or>;
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def XORi : LogicI<0x0e, "xori", xor>;
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def LUi : LoadUpper<0x0f, "lui">;
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/// Arithmetic Instructions (3-Operand, R-Type)
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def ADDu : ArithR<0x00, 0x21, "addu", add, IIAlu>;
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def SUBu : ArithR<0x00, 0x23, "subu", sub, IIAlu>;
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def ADD : ArithOverflowR<0x00, 0x20, "add">;
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def SUB : ArithOverflowR<0x00, 0x22, "sub">;
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// Logical
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def SLT : SetCC_R<0x00, 0x2a, "slt", setlt>;
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def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult>;
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def AND : LogicR<0x24, "and", and>;
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def OR : LogicR<0x25, "or", or>;
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def XOR : LogicR<0x26, "xor", xor>;
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def ANDi : LogicI<0x0c, "andi", and>;
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def ORi : LogicI<0x0d, "ori", or>;
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def XORi : LogicI<0x0e, "xori", xor>;
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def NOR : LogicNOR<0x00, 0x27, "nor">;
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// Shifts
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/// Shift Instructions
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def SLL : LogicR_shift_imm<0x00, "sll", shl>;
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def SRL : LogicR_shift_imm<0x02, "srl", srl>;
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def SRA : LogicR_shift_imm<0x03, "sra", sra>;
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@ -428,10 +423,7 @@ def SLLV : LogicR_shift_reg<0x04, "sllv", shl>;
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def SRLV : LogicR_shift_reg<0x06, "srlv", srl>;
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def SRAV : LogicR_shift_reg<0x07, "srav", sra>;
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// Load Upper Immediate
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def LUi : LoadUpper<0x0f, "lui">;
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// Load/Store
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/// Load and Store Instructions
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def LB : LoadM<0x20, "lb", sextloadi8>;
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def LBu : LoadM<0x24, "lbu", zextloadi8>;
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def LH : LoadM<0x21, "lh", sextloadi16>;
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@ -441,62 +433,54 @@ def SB : StoreM<0x28, "sb", truncstorei8>;
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def SH : StoreM<0x29, "sh", truncstorei16>;
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def SW : StoreM<0x2b, "sw", store>;
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// Conditional Branch
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/// Jump and Branch Instructions
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def J : JumpFJ<0x02, "j">;
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def JR : JumpFR<0x00, 0x08, "jr">;
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def JAL : JumpLink<0x03, "jal">;
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def JALR : JumpLinkReg<0x00, 0x09, "jalr">;
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def BEQ : CBranch<0x04, "beq", seteq>;
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def BNE : CBranch<0x05, "bne", setne>;
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let rt=1 in
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def BGEZ : CBranchZero<0x01, "bgez", setge>;
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def BGEZ : CBranchZero<0x01, "bgez", setge>;
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let rt=0 in {
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def BGTZ : CBranchZero<0x07, "bgtz", setgt>;
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def BLEZ : CBranchZero<0x07, "blez", setle>;
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def BLTZ : CBranchZero<0x01, "bltz", setlt>;
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def BGTZ : CBranchZero<0x07, "bgtz", setgt>;
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def BLEZ : CBranchZero<0x07, "blez", setle>;
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def BLTZ : CBranchZero<0x01, "bltz", setlt>;
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}
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// Set Condition Code
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def SLT : SetCC_R<0x00, 0x2a, "slt", setlt>;
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def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult>;
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def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16>;
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def SLTiu : SetCC_I<0x0b, "sltiu", setult, uimm16, immZExt16>;
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// Unconditional jump
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def J : JumpFJ<0x02, "j">;
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def JR : JumpFR<0x00, 0x08, "jr">;
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// Jump and Link (Call)
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def JAL : JumpLink<0x03, "jal">;
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def JALR : JumpLinkReg<0x00, 0x09, "jalr">;
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def BGEZAL : BranchLink<"bgezal">;
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def BLTZAL : BranchLink<"bltzal">;
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// MulDiv and Move From Hi/Lo operations, have
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// their correpondent SDNodes created on ISelDAG.
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// Special Mul, Div operations
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let isReturn=1, isTerminator=1, hasDelaySlot=1,
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isBarrier=1, hasCtrlDep=1, rs=0, rt=0, shamt=0 in
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def RET : FR <0x00, 0x02, (outs), (ins CPURegs:$target),
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"jr\t$target", [(MipsRet CPURegs:$target)], IIBranch>;
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/// Multiply and Divide Instructions.
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def MULT : MulDiv<0x18, "mult", IIImul>;
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def MULTu : MulDiv<0x19, "multu", IIImul>;
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def DIV : MulDiv<0x1a, "div", IIIdiv>;
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def DIVu : MulDiv<0x1b, "divu", IIIdiv>;
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// Move From Hi/Lo
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def MFHI : MoveFromTo<0x10, "mfhi">;
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def MFLO : MoveFromTo<0x12, "mflo">;
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def MTHI : MoveFromTo<0x11, "mthi">;
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def MTLO : MoveFromTo<0x13, "mtlo">;
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// No operation
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let addr=0 in
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def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>;
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/// Sign Ext In Register Instructions.
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let Predicates = [HasSEInReg] in {
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let shamt = 0x10, rs = 0 in
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def SEB : SignExtInReg<0x21, "seb", i8>;
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// Ret instruction - as mips does not have "ret" a
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// jr $ra must be generated.
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let isReturn=1, isTerminator=1, hasDelaySlot=1,
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isBarrier=1, hasCtrlDep=1, rs=0, rt=0, shamt=0 in
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{
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def RET : FR <0x00, 0x02, (outs), (ins CPURegs:$target),
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"jr\t$target", [(MipsRet CPURegs:$target)], IIBranch>;
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let shamt = 0x18, rs = 0 in
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def SEH : SignExtInReg<0x20, "seh", i16>;
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}
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/// No operation
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let addr=0 in
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def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>;
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// FrameIndexes are legalized when they are operands from load/store
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// instructions. The same not happens for stack address copies, so an
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// add op with mem ComplexPattern is used and the stack address copy
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@ -516,13 +500,9 @@ def LEA_ADDiu : EffectiveAddress<"addiu\t$dst, ${addr:stackloc}">;
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//def MSUB : MArithR<0x04, "msub">;
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//def MSUBU : MArithR<0x05, "msubu">;
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let Predicates = [HasSEInReg] in {
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let shamt = 0x10, rs = 0 in
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def SEB : SignExtInReg<0x21, "seb", i8>;
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let shamt = 0x18, rs = 0 in
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def SEH : SignExtInReg<0x20, "seh", i16>;
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}
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// MUL is a assembly macro in the current used ISAs. In recent ISA's
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// it is a real instruction.
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//def MUL : ArithR<0x1c, 0x02, "mul", mul, IIImul>;
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//===----------------------------------------------------------------------===//
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// Arbitrary patterns that map to one or more instructions
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@ -625,8 +605,8 @@ def : Pat<(brcond (setult CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
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def : Pat<(brcond CPURegs:$cond, bb:$dst),
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(BNE CPURegs:$cond, ZERO, bb:$dst)>;
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/// setcc patterns, only matched when there
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/// is no brcond following a setcc operation
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// setcc patterns, only matched when there
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// is no brcond following a setcc operation
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def : Pat<(setle CPURegs:$lhs, CPURegs:$rhs),
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(XORi (SLT CPURegs:$rhs, CPURegs:$lhs), 1)>;
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def : Pat<(setule CPURegs:$lhs, CPURegs:$rhs),
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