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Minor code simplifications.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77769 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -314,8 +314,8 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
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const TargetInstrInfo &TII = *TM.getInstrInfo();
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const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
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if (MF->getFunction()->hasGC())
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GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(*MF->getFunction());
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if (Fn.hasGC())
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GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn);
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else
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GFI = 0;
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RegInfo = &MF->getRegInfo();
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@ -550,10 +550,10 @@ void SelectionDAGISel::ComputeLiveOutVRegInfo() {
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// Only install this information if it tells us something.
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if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
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DestReg -= TargetRegisterInfo::FirstVirtualRegister;
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FunctionLoweringInfo &FLI = CurDAG->getFunctionLoweringInfo();
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if (DestReg >= FLI.LiveOutRegInfo.size())
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FLI.LiveOutRegInfo.resize(DestReg+1);
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FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[DestReg];
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if (DestReg >= FuncInfo->LiveOutRegInfo.size())
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FuncInfo->LiveOutRegInfo.resize(DestReg+1);
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FunctionLoweringInfo::LiveOutInfo &LOI =
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FuncInfo->LiveOutRegInfo[DestReg];
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LOI.NumSignBits = NumSignBits;
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LOI.KnownOne = KnownOne;
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LOI.KnownZero = KnownZero;
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@ -569,7 +569,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
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if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
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ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
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ViewSUnitDAGs)
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BlockName = CurDAG->getMachineFunction().getFunction()->getNameStr() + ":" +
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BlockName = MF->getFunction()->getNameStr() + ":" +
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BB->getBasicBlock()->getNameStr();
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DOUT << "Initial selection DAG:\n";
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@ -1224,7 +1224,7 @@ SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
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}
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// Add this to the output node.
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MVT IntPtrTy = CurDAG->getTargetLoweringInfo().getPointerTy();
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MVT IntPtrTy = TLI.getPointerTy();
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Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size()<< 3),
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IntPtrTy));
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Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
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