6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-09-24 23:28:41 +00:00
Code Issues Projects Releases Wiki Activity

Expand pseudos BteqzT8CmpiX16 and BtnezT8CmpiX16.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175474 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Reed Kotler
2013-02-19 00:20:58 +00:00
parent 56f58ad0e4
commit f801675207
5 changed files with 256 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

26
lib/Target/Mips/Mips16InstrInfo.cpp
View File

@@ -139,6 +139,10 @@ bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
case Mips::BteqzT8CmpX16:
ExpandFEXT_T8I816_ins(MBB, MI, Mips::BteqzX16, Mips::CmpRxRy16);
break;
case Mips::BteqzT8CmpiX16:
ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BteqzX16,
Mips::CmpiRxImm16, Mips::CmpiRxImmX16);
break;
case Mips::BteqzT8SltX16:
ExpandFEXT_T8I816_ins(MBB, MI, Mips::BteqzX16, Mips::SltRxRy16);
break;
@@ -150,6 +154,10 @@ bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
case Mips::BtnezT8CmpX16:
ExpandFEXT_T8I816_ins(MBB, MI, Mips::BtnezX16, Mips::CmpRxRy16);
break;
case Mips::BtnezT8CmpiX16:
ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BtnezX16,
Mips::CmpiRxImm16, Mips::CmpiRxImmX16);
break;
case Mips::BtnezT8SltX16:
ExpandFEXT_T8I816_ins(MBB, MI, Mips::BtnezX16, Mips::SltRxRy16);
break;
@@ -433,6 +441,24 @@ void Mips16InstrInfo::ExpandFEXT_T8I816_ins(
BuildMI(MBB, I, I->getDebugLoc(), get(BtOpc)).addMBB(target);
}
void Mips16InstrInfo::ExpandFEXT_T8I8I16_ins(
MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc) const {
unsigned regX = I->getOperand(0).getReg();
int64_t imm = I->getOperand(1).getImm();
MachineBasicBlock *target = I->getOperand(2).getMBB();
unsigned CmpOpc;
if (isUInt<8>(imm))
CmpOpc = CmpiOpc;
else if (isUInt<16>(imm))
CmpOpc = CmpiXOpc;
else
llvm_unreachable("immediate field not usable");
BuildMI(MBB, I, I->getDebugLoc(), get(CmpOpc)).addReg(regX).addImm(imm);
BuildMI(MBB, I, I->getDebugLoc(), get(BtOpc)).addMBB(target);
}
const MCInstrDesc &Mips16InstrInfo::AddiuSpImm(int64_t Imm) const {
if (validSpImm8(Imm))
return get(Mips::AddiuSpImm16);