mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-02-07 14:33:15 +00:00
Use the TargetMachine on the DAG or the MachineFunction instead
of using the cached TargetMachine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210589 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher
parent
cd0b8d6cbf
commit
f85ae2a8c2
@ -1732,7 +1732,7 @@ const MCExpr *
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X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
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const MachineBasicBlock *MBB,
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unsigned uid,MCContext &Ctx) const{
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assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
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assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
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Subtarget->isPICStyleGOT());
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// In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
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// entries.
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@ -1831,7 +1831,7 @@ X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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LLVMContext &Context) const {
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SmallVector<CCValAssign, 16> RVLocs;
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CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
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CCState CCInfo(CallConv, isVarArg, MF, MF.getTarget(),
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RVLocs, Context);
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return CCInfo.CheckReturn(Outs, RetCC_X86);
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}
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@ -1851,7 +1851,7 @@ X86TargetLowering::LowerReturn(SDValue Chain,
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X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
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SmallVector<CCValAssign, 16> RVLocs;
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CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
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CCState CCInfo(CallConv, isVarArg, MF, DAG.getTarget(),
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RVLocs, *DAG.getContext());
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CCInfo.AnalyzeReturn(Outs, RetCC_X86);
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@ -2023,7 +2023,7 @@ X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
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SmallVector<CCValAssign, 16> RVLocs;
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bool Is64Bit = Subtarget->is64Bit();
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CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
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getTargetMachine(), RVLocs, *DAG.getContext());
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DAG.getTarget(), RVLocs, *DAG.getContext());
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CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
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// Copy all of the result registers out of their specified physreg.
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@ -2173,8 +2173,8 @@ X86TargetLowering::LowerMemArgument(SDValue Chain,
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unsigned i) const {
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// Create the nodes corresponding to a load from this parameter slot.
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ISD::ArgFlagsTy Flags = Ins[i].Flags;
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bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
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getTargetMachine().Options.GuaranteedTailCallOpt);
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bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
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CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
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bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
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EVT ValVT;
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@ -2231,7 +2231,7 @@ X86TargetLowering::LowerFormalArguments(SDValue Chain,
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// Assign locations to all of the incoming arguments.
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
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CCState CCInfo(CallConv, isVarArg, MF, DAG.getTarget(),
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ArgLocs, *DAG.getContext());
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// Allocate shadow area for Win64
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@ -2395,7 +2395,7 @@ X86TargetLowering::LowerFormalArguments(SDValue Chain,
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TotalNumXMMRegs = 0;
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if (IsWin64) {
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const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
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const TargetFrameLowering &TFI = *MF.getTarget().getFrameLowering();
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// Get to the caller-allocated home save location. Add 8 to account
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// for the return address.
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int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
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@ -2594,7 +2594,7 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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// Analyze operands of the call, assigning locations to each operand.
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
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CCState CCInfo(CallConv, isVarArg, MF, MF.getTarget(),
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ArgLocs, *DAG.getContext());
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// Allocate shadow area for Win64
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@ -2609,7 +2609,7 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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// This is a sibcall. The memory operands are available in caller's
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// own caller's stack.
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NumBytes = 0;
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else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
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else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
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IsTailCallConvention(CallConv))
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NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
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@ -2656,7 +2656,7 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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// Walk the register/memloc assignments, inserting copies/loads. In the case
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// of tail call optimization arguments are handle later.
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const X86RegisterInfo *RegInfo =
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static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
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static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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// Skip inalloca arguments, they have already been written.
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ISD::ArgFlagsTy Flags = Outs[i].Flags;
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@ -2847,7 +2847,7 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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InFlag = Chain.getValue(1);
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}
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if (getTargetMachine().getCodeModel() == CodeModel::Large) {
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if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
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assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
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// In the 64-bit large code model, we have to make all calls
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// through a register, since the call instruction's 32-bit
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@ -2871,7 +2871,7 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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// has hidden or protected visibility, or if it is static or local, then
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// we don't need to use the PLT - we can directly call it.
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if (Subtarget->isTargetELF() &&
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getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
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DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
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GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
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OpFlags = X86II::MO_PLT;
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} else if (Subtarget->isPICStyleStubAny() &&
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@ -2913,7 +2913,7 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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// On ELF targets, in either X86-64 or X86-32 mode, direct calls to
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// external symbols should go through the PLT.
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if (Subtarget->isTargetELF() &&
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getTargetMachine().getRelocationModel() == Reloc::PIC_) {
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DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
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OpFlags = X86II::MO_PLT;
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} else if (Subtarget->isPICStyleStubAny() &&
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(!Subtarget->getTargetTriple().isMacOSX() ||
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@ -2952,7 +2952,7 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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RegsToPass[i].second.getValueType()));
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// Add a register mask operand representing the call-preserved registers.
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const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
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const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
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const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
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assert(Mask && "Missing call preserved mask for calling convention");
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Ops.push_back(DAG.getRegisterMask(Mask));
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@ -2976,7 +2976,7 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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// Create the CALLSEQ_END node.
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unsigned NumBytesForCalleeToPop;
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if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
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getTargetMachine().Options.GuaranteedTailCallOpt))
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DAG.getTarget().Options.GuaranteedTailCallOpt))
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NumBytesForCalleeToPop = NumBytes; // Callee pops everything
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else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
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!Subtarget->getTargetTriple().isOSMSVCRT() &&
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@ -3147,7 +3147,7 @@ X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
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bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
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bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
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if (getTargetMachine().Options.GuaranteedTailCallOpt) {
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if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
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if (IsTailCallConvention(CalleeCC) && CCMatch)
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return true;
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return false;
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@ -3159,7 +3159,7 @@ X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
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// Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
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// emit a special epilogue.
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const X86RegisterInfo *RegInfo =
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static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
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static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
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if (RegInfo->needsStackRealignment(MF))
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return false;
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@ -3188,7 +3188,7 @@ X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
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getTargetMachine(), ArgLocs, *DAG.getContext());
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DAG.getTarget(), ArgLocs, *DAG.getContext());
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CCInfo.AnalyzeCallOperands(Outs, CC_X86);
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
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@ -3209,7 +3209,7 @@ X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
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if (Unused) {
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SmallVector<CCValAssign, 16> RVLocs;
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CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
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getTargetMachine(), RVLocs, *DAG.getContext());
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DAG.getTarget(), RVLocs, *DAG.getContext());
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CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
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for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
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CCValAssign &VA = RVLocs[i];
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@ -3223,12 +3223,12 @@ X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
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if (!CCMatch) {
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SmallVector<CCValAssign, 16> RVLocs1;
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CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
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getTargetMachine(), RVLocs1, *DAG.getContext());
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DAG.getTarget(), RVLocs1, *DAG.getContext());
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CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
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SmallVector<CCValAssign, 16> RVLocs2;
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CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
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getTargetMachine(), RVLocs2, *DAG.getContext());
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DAG.getTarget(), RVLocs2, *DAG.getContext());
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CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
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if (RVLocs1.size() != RVLocs2.size())
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@ -3255,7 +3255,7 @@ X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
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// argument is passed on the stack.
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
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getTargetMachine(), ArgLocs, *DAG.getContext());
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DAG.getTarget(), ArgLocs, *DAG.getContext());
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// Allocate shadow area for Win64
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if (IsCalleeWin64)
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@ -3272,7 +3272,7 @@ X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
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MachineFrameInfo *MFI = MF.getFrameInfo();
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const MachineRegisterInfo *MRI = &MF.getRegInfo();
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const X86InstrInfo *TII =
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((const X86TargetMachine&)getTargetMachine()).getInstrInfo();
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static_cast<const X86InstrInfo *>(DAG.getTarget().getInstrInfo());
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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CCValAssign &VA = ArgLocs[i];
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SDValue Arg = OutVals[i];
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@ -3295,12 +3295,12 @@ X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
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if (!Subtarget->is64Bit() &&
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((!isa<GlobalAddressSDNode>(Callee) &&
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!isa<ExternalSymbolSDNode>(Callee)) ||
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getTargetMachine().getRelocationModel() == Reloc::PIC_)) {
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DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
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unsigned NumInRegs = 0;
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// In PIC we need an extra register to formulate the address computation
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// for the callee.
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unsigned MaxInRegs =
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(getTargetMachine().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
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(DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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CCValAssign &VA = ArgLocs[i];
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@ -3424,7 +3424,7 @@ static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
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SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
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MachineFunction &MF = DAG.getMachineFunction();
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const X86RegisterInfo *RegInfo =
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static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
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static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
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X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
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int ReturnAddrIndex = FuncInfo->getRAIndex();
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@ -8665,7 +8665,7 @@ X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
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// global base reg.
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unsigned char OpFlag = 0;
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unsigned WrapperKind = X86ISD::Wrapper;
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CodeModel::Model M = getTargetMachine().getCodeModel();
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CodeModel::Model M = DAG.getTarget().getCodeModel();
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if (Subtarget->isPICStyleRIPRel() &&
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(M == CodeModel::Small || M == CodeModel::Kernel))
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@ -8698,7 +8698,7 @@ SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
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// global base reg.
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unsigned char OpFlag = 0;
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unsigned WrapperKind = X86ISD::Wrapper;
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CodeModel::Model M = getTargetMachine().getCodeModel();
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CodeModel::Model M = DAG.getTarget().getCodeModel();
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if (Subtarget->isPICStyleRIPRel() &&
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(M == CodeModel::Small || M == CodeModel::Kernel))
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@ -8731,7 +8731,7 @@ X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
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// global base reg.
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unsigned char OpFlag = 0;
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unsigned WrapperKind = X86ISD::Wrapper;
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CodeModel::Model M = getTargetMachine().getCodeModel();
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CodeModel::Model M = DAG.getTarget().getCodeModel();
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if (Subtarget->isPICStyleRIPRel() &&
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(M == CodeModel::Small || M == CodeModel::Kernel)) {
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@ -8752,7 +8752,7 @@ X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
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Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
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// With PIC, the address is actually $g + Offset.
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if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
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if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
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!Subtarget->is64Bit()) {
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Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
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DAG.getNode(X86ISD::GlobalBaseReg,
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@ -8774,7 +8774,7 @@ X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
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// Create the TargetBlockAddressAddress node.
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unsigned char OpFlags =
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Subtarget->ClassifyBlockAddressReference();
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CodeModel::Model M = getTargetMachine().getCodeModel();
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CodeModel::Model M = DAG.getTarget().getCodeModel();
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const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
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int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
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SDLoc dl(Op);
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@ -8803,8 +8803,8 @@ X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
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// Create the TargetGlobalAddress node, folding in the constant
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// offset if it is legal.
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unsigned char OpFlags =
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Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
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CodeModel::Model M = getTargetMachine().getCodeModel();
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Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
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CodeModel::Model M = DAG.getTarget().getCodeModel();
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SDValue Result;
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if (OpFlags == X86II::MO_NO_FLAG &&
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X86::isOffsetSuitableForCodeModel(Offset, M)) {
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@ -9003,7 +9003,7 @@ X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
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const GlobalValue *GV = GA->getGlobal();
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if (Subtarget->isTargetELF()) {
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TLSModel::Model model = getTargetMachine().getTLSModel(GV);
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TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
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switch (model) {
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case TLSModel::GeneralDynamic:
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@ -9015,9 +9015,9 @@ X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
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Subtarget->is64Bit());
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case TLSModel::InitialExec:
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case TLSModel::LocalExec:
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return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
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Subtarget->is64Bit(),
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getTargetMachine().getRelocationModel() == Reloc::PIC_);
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return LowerToTLSExecModel(
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GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
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DAG.getTarget().getRelocationModel() == Reloc::PIC_);
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}
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llvm_unreachable("Unknown TLS model.");
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}
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@ -9030,8 +9030,8 @@ X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
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// In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
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// global base reg.
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bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
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!Subtarget->is64Bit();
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bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
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!Subtarget->is64Bit();
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if (PIC32)
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OpFlag = X86II::MO_TLVP_PIC_BASE;
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else
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@ -11666,7 +11666,7 @@ X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
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SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
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Chain = SP.getValue(1);
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unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
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const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
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const TargetFrameLowering &TFI = *DAG.getTarget().getFrameLowering();
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unsigned StackAlign = TFI.getStackAlignment();
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Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
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if (Align > StackAlign)
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@ -11725,7 +11725,7 @@ X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
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Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
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const X86RegisterInfo *RegInfo =
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static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
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static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
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unsigned SPReg = RegInfo->getStackRegister();
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SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
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Chain = SP.getValue(1);
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@ -11834,7 +11834,7 @@ SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
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if (ArgMode == 2) {
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// Sanity Check: Make sure using fp_offset makes sense.
|
||||
assert(!getTargetMachine().Options.UseSoftFloat &&
|
||||
assert(!DAG.getTarget().Options.UseSoftFloat &&
|
||||
!(DAG.getMachineFunction()
|
||||
.getFunction()->getAttributes()
|
||||
.hasAttribute(AttributeSet::FunctionIndex,
|
||||
@ -13026,7 +13026,7 @@ SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
|
||||
if (Depth > 0) {
|
||||
SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
|
||||
const X86RegisterInfo *RegInfo =
|
||||
static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
|
||||
static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
|
||||
SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
|
||||
return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
|
||||
DAG.getNode(ISD::ADD, dl, PtrVT,
|
||||
@ -13048,7 +13048,7 @@ SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
|
||||
SDLoc dl(Op); // FIXME probably not meaningful
|
||||
unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
|
||||
const X86RegisterInfo *RegInfo =
|
||||
static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
|
||||
static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
|
||||
unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
|
||||
assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
|
||||
(FrameReg == X86::EBP && VT == MVT::i32)) &&
|
||||
@ -13077,7 +13077,7 @@ unsigned X86TargetLowering::getRegisterByName(const char* RegName,
|
||||
SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
|
||||
SelectionDAG &DAG) const {
|
||||
const X86RegisterInfo *RegInfo =
|
||||
static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
|
||||
static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
|
||||
return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
|
||||
}
|
||||
|
||||
@ -13089,7 +13089,7 @@ SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
|
||||
|
||||
EVT PtrVT = getPointerTy();
|
||||
const X86RegisterInfo *RegInfo =
|
||||
static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
|
||||
static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
|
||||
unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
|
||||
assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
|
||||
(FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
|
||||
@ -13136,7 +13136,7 @@ SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
|
||||
SDLoc dl (Op);
|
||||
|
||||
const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
|
||||
const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
|
||||
const TargetRegisterInfo* TRI = DAG.getTarget().getRegisterInfo();
|
||||
|
||||
if (Subtarget->is64Bit()) {
|
||||
SDValue OutChains[6];
|
||||
@ -15552,10 +15552,10 @@ static unsigned getPseudoCMOVOpc(EVT VT) {
|
||||
MachineBasicBlock *
|
||||
X86TargetLowering::EmitAtomicLoadArith(MachineInstr *MI,
|
||||
MachineBasicBlock *MBB) const {
|
||||
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
|
||||
MachineFunction *MF = MBB->getParent();
|
||||
const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
|
||||
DebugLoc DL = MI->getDebugLoc();
|
||||
|
||||
MachineFunction *MF = MBB->getParent();
|
||||
MachineRegisterInfo &MRI = MF->getRegInfo();
|
||||
|
||||
const BasicBlock *BB = MBB->getBasicBlock();
|
||||
@ -15713,7 +15713,7 @@ X86TargetLowering::EmitAtomicLoadArith(MachineInstr *MI,
|
||||
.addReg(t4);
|
||||
} else {
|
||||
// Promote i8 to i32 to use CMOV32
|
||||
const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
|
||||
const TargetRegisterInfo* TRI = MF->getTarget().getRegisterInfo();
|
||||
const TargetRegisterClass *RC32 =
|
||||
TRI->getSubClassWithSubReg(getRegClassFor(MVT::i32), X86::sub_8bit);
|
||||
unsigned SrcReg32 = MRI.createVirtualRegister(RC32);
|
||||
@ -15825,10 +15825,10 @@ X86TargetLowering::EmitAtomicLoadArith(MachineInstr *MI,
|
||||
MachineBasicBlock *
|
||||
X86TargetLowering::EmitAtomicLoadArith6432(MachineInstr *MI,
|
||||
MachineBasicBlock *MBB) const {
|
||||
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
|
||||
MachineFunction *MF = MBB->getParent();
|
||||
const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
|
||||
DebugLoc DL = MI->getDebugLoc();
|
||||
|
||||
MachineFunction *MF = MBB->getParent();
|
||||
MachineRegisterInfo &MRI = MF->getRegInfo();
|
||||
|
||||
const BasicBlock *BB = MBB->getBasicBlock();
|
||||
@ -16222,7 +16222,7 @@ X86TargetLowering::EmitVAARG64WithCustomInserter(
|
||||
MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
|
||||
|
||||
// Machine Information
|
||||
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
|
||||
const TargetInstrInfo *TII = MBB->getParent()->getTarget().getInstrInfo();
|
||||
MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
|
||||
const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
|
||||
const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
|
||||
@ -16478,7 +16478,7 @@ X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
|
||||
XMMSaveMBB->addSuccessor(EndMBB);
|
||||
|
||||
// Now add the instructions.
|
||||
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
|
||||
const TargetInstrInfo *TII = MBB->getParent()->getTarget().getInstrInfo();
|
||||
DebugLoc DL = MI->getDebugLoc();
|
||||
|
||||
unsigned CountReg = MI->getOperand(0).getReg();
|
||||
@ -16561,7 +16561,7 @@ static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
|
||||
MachineBasicBlock *
|
||||
X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
|
||||
MachineBasicBlock *BB) const {
|
||||
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
|
||||
const TargetInstrInfo *TII = BB->getParent()->getTarget().getInstrInfo();
|
||||
DebugLoc DL = MI->getDebugLoc();
|
||||
|
||||
// To "insert" a SELECT_CC instruction, we actually have to insert the
|
||||
@ -16587,7 +16587,7 @@ X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
|
||||
|
||||
// If the EFLAGS register isn't dead in the terminator, then claim that it's
|
||||
// live into the sink and copy blocks.
|
||||
const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
|
||||
const TargetRegisterInfo* TRI = BB->getParent()->getTarget().getRegisterInfo();
|
||||
if (!MI->killsRegister(X86::EFLAGS) &&
|
||||
!checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
|
||||
copy0MBB->addLiveIn(X86::EFLAGS);
|
||||
@ -16628,9 +16628,9 @@ X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
|
||||
MachineBasicBlock *
|
||||
X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
|
||||
bool Is64Bit) const {
|
||||
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
|
||||
DebugLoc DL = MI->getDebugLoc();
|
||||
MachineFunction *MF = BB->getParent();
|
||||
const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
|
||||
DebugLoc DL = MI->getDebugLoc();
|
||||
const BasicBlock *LLVM_BB = BB->getBasicBlock();
|
||||
|
||||
assert(MF->shouldSplitStack());
|
||||
@ -16700,7 +16700,7 @@ X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
|
||||
|
||||
// Calls into a routine in libgcc to allocate more space from the heap.
|
||||
const uint32_t *RegMask =
|
||||
getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
|
||||
MF->getTarget().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
|
||||
if (Is64Bit) {
|
||||
BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
|
||||
.addReg(sizeVReg);
|
||||
@ -16748,8 +16748,8 @@ X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
|
||||
|
||||
MachineBasicBlock *
|
||||
X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
|
||||
MachineBasicBlock *BB) const {
|
||||
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
|
||||
MachineBasicBlock *BB) const {
|
||||
const TargetInstrInfo *TII = BB->getParent()->getTarget().getInstrInfo();
|
||||
DebugLoc DL = MI->getDebugLoc();
|
||||
|
||||
assert(!Subtarget->isTargetMacho());
|
||||
@ -16805,10 +16805,10 @@ X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
|
||||
// our load from the relocation, sticking it in either RDI (x86-64)
|
||||
// or EAX and doing an indirect call. The return value will then
|
||||
// be in the normal return register.
|
||||
const X86InstrInfo *TII
|
||||
= static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
|
||||
DebugLoc DL = MI->getDebugLoc();
|
||||
MachineFunction *F = BB->getParent();
|
||||
const X86InstrInfo *TII
|
||||
= static_cast<const X86InstrInfo*>(F->getTarget().getInstrInfo());
|
||||
DebugLoc DL = MI->getDebugLoc();
|
||||
|
||||
assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
|
||||
assert(MI->getOperand(3).isGlobal() && "This should be a global");
|
||||
@ -16817,7 +16817,7 @@ X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
|
||||
// FIXME: The 32-bit calls have non-standard calling conventions. Use a
|
||||
// proper register mask.
|
||||
const uint32_t *RegMask =
|
||||
getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
|
||||
F->getTarget().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
|
||||
if (Subtarget->is64Bit()) {
|
||||
MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
|
||||
TII->get(X86::MOV64rm), X86::RDI)
|
||||
@ -16829,7 +16829,7 @@ X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
|
||||
MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
|
||||
addDirectMem(MIB, X86::RDI);
|
||||
MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
|
||||
} else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
|
||||
} else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
|
||||
MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
|
||||
TII->get(X86::MOV32rm), X86::EAX)
|
||||
.addReg(0)
|
||||
@ -16861,9 +16861,8 @@ MachineBasicBlock *
|
||||
X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
|
||||
MachineBasicBlock *MBB) const {
|
||||
DebugLoc DL = MI->getDebugLoc();
|
||||
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
|
||||
|
||||
MachineFunction *MF = MBB->getParent();
|
||||
const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
|
||||
MachineRegisterInfo &MRI = MF->getRegInfo();
|
||||
|
||||
const BasicBlock *BB = MBB->getBasicBlock();
|
||||
@ -16925,8 +16924,8 @@ X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
|
||||
unsigned PtrStoreOpc = 0;
|
||||
unsigned LabelReg = 0;
|
||||
const int64_t LabelOffset = 1 * PVT.getStoreSize();
|
||||
Reloc::Model RM = getTargetMachine().getRelocationModel();
|
||||
bool UseImmLabel = (getTargetMachine().getCodeModel() == CodeModel::Small) &&
|
||||
Reloc::Model RM = MF->getTarget().getRelocationModel();
|
||||
bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
|
||||
(RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
|
||||
|
||||
// Prepare IP either in reg or imm.
|
||||
@ -16970,7 +16969,7 @@ X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
|
||||
.addMBB(restoreMBB);
|
||||
|
||||
const X86RegisterInfo *RegInfo =
|
||||
static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
|
||||
static_cast<const X86RegisterInfo*>(MF->getTarget().getRegisterInfo());
|
||||
MIB.addRegMask(RegInfo->getNoPreservedMask());
|
||||
thisMBB->addSuccessor(mainMBB);
|
||||
thisMBB->addSuccessor(restoreMBB);
|
||||
@ -16999,9 +16998,8 @@ MachineBasicBlock *
|
||||
X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
|
||||
MachineBasicBlock *MBB) const {
|
||||
DebugLoc DL = MI->getDebugLoc();
|
||||
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
|
||||
|
||||
MachineFunction *MF = MBB->getParent();
|
||||
const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
|
||||
MachineRegisterInfo &MRI = MF->getRegInfo();
|
||||
|
||||
// Memory Reference
|
||||
@ -17017,7 +17015,7 @@ X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
|
||||
unsigned Tmp = MRI.createVirtualRegister(RC);
|
||||
// Since FP is only updated here but NOT referenced, it's treated as GPR.
|
||||
const X86RegisterInfo *RegInfo =
|
||||
static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
|
||||
static_cast<const X86RegisterInfo*>(MF->getTarget().getRegisterInfo());
|
||||
unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
|
||||
unsigned SP = RegInfo->getStackRegister();
|
||||
|
||||
@ -17192,12 +17190,12 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
|
||||
case X86::FP80_TO_INT16_IN_MEM:
|
||||
case X86::FP80_TO_INT32_IN_MEM:
|
||||
case X86::FP80_TO_INT64_IN_MEM: {
|
||||
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
|
||||
MachineFunction *F = BB->getParent();
|
||||
const TargetInstrInfo *TII = F->getTarget().getInstrInfo();
|
||||
DebugLoc DL = MI->getDebugLoc();
|
||||
|
||||
// Change the floating point control register to use "round towards zero"
|
||||
// mode when truncating to an integer value.
|
||||
MachineFunction *F = BB->getParent();
|
||||
int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
|
||||
addFrameReference(BuildMI(*BB, MI, DL,
|
||||
TII->get(X86::FNSTCW16m)), CWFrameIdx);
|
||||
@ -17277,7 +17275,7 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
|
||||
case X86::VPCMPESTRM128MEM:
|
||||
assert(Subtarget->hasSSE42() &&
|
||||
"Target must have SSE4.2 or AVX features enabled");
|
||||
return EmitPCMPSTRM(MI, BB, getTargetMachine().getInstrInfo());
|
||||
return EmitPCMPSTRM(MI, BB, BB->getParent()->getTarget().getInstrInfo());
|
||||
|
||||
// String/text processing lowering.
|
||||
case X86::PCMPISTRIREG:
|
||||
@ -17290,15 +17288,15 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
|
||||
case X86::VPCMPESTRIMEM:
|
||||
assert(Subtarget->hasSSE42() &&
|
||||
"Target must have SSE4.2 or AVX features enabled");
|
||||
return EmitPCMPSTRI(MI, BB, getTargetMachine().getInstrInfo());
|
||||
return EmitPCMPSTRI(MI, BB, BB->getParent()->getTarget().getInstrInfo());
|
||||
|
||||
// Thread synchronization.
|
||||
case X86::MONITOR:
|
||||
return EmitMonitor(MI, BB, getTargetMachine().getInstrInfo(), Subtarget);
|
||||
return EmitMonitor(MI, BB, BB->getParent()->getTarget().getInstrInfo(), Subtarget);
|
||||
|
||||
// xbegin
|
||||
case X86::XBEGIN:
|
||||
return EmitXBegin(MI, BB, getTargetMachine().getInstrInfo());
|
||||
return EmitXBegin(MI, BB, BB->getParent()->getTarget().getInstrInfo());
|
||||
|
||||
// Atomic Lowering.
|
||||
case X86::ATOMAND8:
|
||||
@ -21354,8 +21352,8 @@ void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
|
||||
const GlobalValue *GV = GA->getGlobal();
|
||||
// If we require an extra load to get this address, as in PIC mode, we
|
||||
// can't accept it.
|
||||
if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
|
||||
getTargetMachine())))
|
||||
if (isGlobalStubReference(
|
||||
Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
|
||||
return;
|
||||
|
||||
Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user