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Prefer larger register classes over smaller ones when a register occurs in

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multiple register classes.  This fixes PowerPC/2006-04-01-FloatDoubleExtend.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27334 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-04-02 00:24:45 +00:00
parent 4502e13c9b
commit f8814cf8b8
1 changed files with 21 additions and 7 deletions
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28
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
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@ -1663,21 +1663,30 @@ void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
static const TargetRegisterClass * static const TargetRegisterClass *
isAllocatableRegister(unsigned Reg, MachineFunction &MF, isAllocatableRegister(unsigned Reg, MachineFunction &MF,
const TargetLowering &TLI, const MRegisterInfo *MRI) { const TargetLowering &TLI, const MRegisterInfo *MRI) {
MVT::ValueType FoundVT = MVT::Other;
const TargetRegisterClass *FoundRC = 0;
for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(), for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(),
E = MRI->regclass_end(); RCI != E; ++RCI) { E = MRI->regclass_end(); RCI != E; ++RCI) {
MVT::ValueType ThisVT = MVT::Other;
const TargetRegisterClass *RC = *RCI; const TargetRegisterClass *RC = *RCI;
// If none of the the value types for this register class are valid, we // If none of the the value types for this register class are valid, we
// can't use it. For example, 64-bit reg classes on 32-bit targets. // can't use it. For example, 64-bit reg classes on 32-bit targets.
bool isLegal = false;
for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
I != E; ++I) { I != E; ++I) {
if (TLI.isTypeLegal(*I)) { if (TLI.isTypeLegal(*I)) {
isLegal = true; // If we have already found this register in a different register class,
break; // choose the one with the largest VT specified. For example, on
// PowerPC, we favor f64 register classes over f32.
if (FoundVT == MVT::Other ||
MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) {
ThisVT = *I;
break;
}
} }
} }
if (!isLegal) continue; if (ThisVT == MVT::Other) continue;
// NOTE: This isn't ideal. In particular, this might allocate the // NOTE: This isn't ideal. In particular, this might allocate the
// frame pointer in functions that need it (due to them not being taken // frame pointer in functions that need it (due to them not being taken
@ -1685,10 +1694,15 @@ isAllocatableRegister(unsigned Reg, MachineFunction &MF,
// yet). This is a slight code pessimization, but should still work. // yet). This is a slight code pessimization, but should still work.
for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
E = RC->allocation_order_end(MF); I != E; ++I) E = RC->allocation_order_end(MF); I != E; ++I)
if (*I == Reg) if (*I == Reg) {
return RC; // We found a matching register class. Keep looking at others in case
// we find one with larger registers that this physreg is also in.
FoundRC = RC;
FoundVT = ThisVT;
break;
}
} }
return 0; return FoundRC;
} }
RegsForValue SelectionDAGLowering:: RegsForValue SelectionDAGLowering::