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Make pattern isel default for ppc

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Add new ppc beta option related to using condition registers
Make pattern isel control flag (-enable-pattern-isel) global and tristate
  0 == off
  1 == on
  2 == target default


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21309 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman
2005-04-15 22:12:16 +00:00
parent da3f296854
commit f8b02949e3
6 changed files with 43 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
lib/Target/PowerPC/PPC.h
View File

@@ -29,6 +29,7 @@ FunctionPass *createPPC64ISelPattern(TargetMachine &TM);
FunctionPass *createDarwinAsmPrinter(std::ostream &OS, TargetMachine &TM);
FunctionPass *createAIXAsmPrinter(std::ostream &OS, TargetMachine &TM);
extern bool PPCCRopts;
} // end namespace llvm;
// GCC #defines PPC on Linux but we use it as our namespace name

5
lib/Target/PowerPC/PPCISelPattern.cpp
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@@ -1067,7 +1067,7 @@ unsigned ISel::SelectCC(SDOperand CC, unsigned &Opc) {
BuildMI(BB, CompareOpc, 2, Result).addReg(Tmp1).addReg(Tmp2);
}
} else {
#if 0
if (PPCCRopts)
if (CC.getOpcode() == ISD::AND || CC.getOpcode() == ISD::OR)
if (CC.getOperand(0).Val->hasOneUse() &&
CC.getOperand(1).Val->hasOneUse()) {
@@ -1093,7 +1093,6 @@ unsigned ISel::SelectCC(SDOperand CC, unsigned &Opc) {
return Result;
}
}
#endif
Opc = PPC::BNE;
Tmp1 = SelectExpr(CC);
BuildMI(BB, PPC::CMPLWI, 2, Result).addReg(Tmp1).addImm(0);
@@ -1127,7 +1126,7 @@ void ISel::SelectBranchCC(SDOperand N)
unsigned Opc, CCReg;
Select(N.getOperand(0)); //chain
CCReg = SelectCC(N.getOperand(1), Opc);
// Iterate to the next basic block, unless we're already at the end of the
ilist<MachineBasicBlock>::iterator It = BB, E = BB->getParent()->end();
if (++It == E) It = BB;

29
lib/Target/PowerPC/PPCTargetMachine.cpp
View File

@@ -30,15 +30,18 @@
using namespace llvm;
namespace llvm {
bool PPCCRopts;
cl::opt<bool> AIX("aix",
cl::desc("Generate AIX/xcoff instead of Darwin/MachO"),
cl::Hidden);
cl::opt<bool> EnablePPCLSR("enable-lsr-for-ppc",
cl::desc("Enable LSR for PPC (beta option!)"),
cl::desc("Enable LSR for PPC (beta)"),
cl::Hidden);
cl::opt<bool> EnablePatternISel("enable-ppc-pattern-isel", cl::Hidden,
cl::desc("Enable the pattern isel"));
cl::opt<bool, true> EnablePPCCRopts("enable-cc-opts",
cl::desc("Enable opts using condition regs (beta)"),
cl::location(PPCCRopts),
cl::init(false),
cl::Hidden);
}
namespace {
@@ -96,12 +99,13 @@ bool PowerPCTargetMachine::addPassesToEmitAssembly(PassManager &PM,
// Make sure that no unreachable blocks are instruction selected.
PM.add(createUnreachableBlockEliminationPass());
// Default to pattern ISel
if (LP64)
PM.add(createPPC64ISelPattern(*this));
else if (EnablePatternISel)
PM.add(createPPC32ISelPattern(*this));
else
else if (PatternISelTriState == 0)
PM.add(createPPC32ISelSimple(*this));
else
PM.add(createPPC32ISelPattern(*this));
if (PrintMachineCode)
PM.add(createMachineFunctionPrinterPass(&std::cerr));
@@ -126,6 +130,8 @@ bool PowerPCTargetMachine::addPassesToEmitAssembly(PassManager &PM,
}
void PowerPCJITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
bool LP64 = (0 != dynamic_cast<PPC64TargetMachine *>(&TM));
if (EnablePPCLSR) {
PM.add(createLoopStrengthReducePass());
PM.add(createCFGSimplificationPass());
@@ -145,7 +151,14 @@ void PowerPCJITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
// Make sure that no unreachable blocks are instruction selected.
PM.add(createUnreachableBlockEliminationPass());
PM.add(createPPC32ISelSimple(TM));
// Default to pattern ISel
if (LP64)
PM.add(createPPC64ISelPattern(TM));
else if (PatternISelTriState == 0)
PM.add(createPPC32ISelSimple(TM));
else
PM.add(createPPC32ISelPattern(TM));
PM.add(createRegisterAllocator());
PM.add(createPrologEpilogCodeInserter());