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https://github.com/c64scene-ar/llvm-6502.git
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CodeGen: emit IR-level f16 conversion intrinsics as fptrunc/fpext
This makes the first stage DAG for @llvm.convert.to.fp16 an fptrunc, and correspondingly @llvm.convert.from.fp16 an fpext. The legalisation path is now uniform, regardless of the input IR: fptrunc -> FP_TO_FP16 (if f16 illegal) -> libcall fpext -> FP16_TO_FP (if f16 illegal) -> libcall Each target should be able to select the version that best matches its operations and not be required to duplicate patterns for both fptrunc and FP_TO_FP16 (for example). As a result we can remove some redundant AArch64 patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213507 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover
parent
d4cde8670c
commit
f8d927f22b
@ -373,6 +373,13 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FNEG(SDNode *N) {
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SDValue DAGTypeLegalizer::SoftenFloatRes_FP_EXTEND(SDNode *N) {
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EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
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SDValue Op = N->getOperand(0);
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// There's only a libcall for f16 -> f32, so proceed in two stages. Also, it's
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// entirely possible for both f16 and f32 to be legal, so use the fully
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// hard-float FP_EXTEND rather than FP16_TO_FP.
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if (Op.getValueType() == MVT::f16 && N->getValueType(0) != MVT::f32)
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Op = DAG.getNode(ISD::FP_EXTEND, SDLoc(N), MVT::f32, Op);
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RTLIB::Libcall LC = RTLIB::getFPEXT(Op.getValueType(), N->getValueType(0));
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assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!");
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return TLI.makeLibCall(DAG, LC, NVT, &Op, 1, false, SDLoc(N)).first;
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@ -511,6 +518,9 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FSUB(SDNode *N) {
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SDValue DAGTypeLegalizer::SoftenFloatRes_FTRUNC(SDNode *N) {
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EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
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if (N->getValueType(0) == MVT::f16)
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return DAG.getNode(ISD::FP_TO_FP16, SDLoc(N), NVT, N->getOperand(0));
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SDValue Op = GetSoftenedFloat(N->getOperand(0));
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return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
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RTLIB::TRUNC_F32,
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@ -5155,13 +5155,16 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
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return nullptr;
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}
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case Intrinsic::convert_to_fp16:
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setValue(&I, DAG.getNode(ISD::FP_TO_FP16, sdl,
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MVT::i16, getValue(I.getArgOperand(0))));
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setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
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DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
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getValue(I.getArgOperand(0)),
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DAG.getTargetConstant(0, MVT::i32))));
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return nullptr;
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case Intrinsic::convert_from_fp16:
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setValue(&I,
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DAG.getNode(ISD::FP16_TO_FP, sdl, TLI->getValueType(I.getType()),
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getValue(I.getArgOperand(0))));
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DAG.getNode(ISD::FP_EXTEND, sdl, TLI->getValueType(I.getType()),
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DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
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getValue(I.getArgOperand(0)))));
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return nullptr;
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case Intrinsic::pcmarker: {
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SDValue Tmp = getValue(I.getArgOperand(0));
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@ -422,7 +422,10 @@ static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
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/// getFPEXT - Return the FPEXT_*_* value for the given types, or
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/// UNKNOWN_LIBCALL if there is none.
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RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
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if (OpVT == MVT::f32) {
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if (OpVT == MVT::f16) {
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if (RetVT == MVT::f32)
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return FPEXT_F16_F32;
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} else if (OpVT == MVT::f32) {
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if (RetVT == MVT::f64)
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return FPEXT_F32_F64;
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if (RetVT == MVT::f128)
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@ -2244,90 +2244,6 @@ def : Pat<(f64 (fpimm0)), (FMOVXDr XZR)>, Requires<[NoZCZ]>;
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defm FCVT : FPConversion<"fcvt">;
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def : Pat<(fp_to_f16 FPR32:$Rn),
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(i32 (COPY_TO_REGCLASS
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(f32 (SUBREG_TO_REG (i32 0), (FCVTHSr FPR32:$Rn), hsub)),
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GPR32))>;
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def : Pat<(f32 (f16_to_fp i32:$Rn)),
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(FCVTSHr (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS i32:$Rn, FPR32)),
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hsub))>;
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// When converting from f16 coming directly from a load, make sure we
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// load into the FPR16 registers rather than going through the GPRs.
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// f16->f32
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def : Pat<(f32 (f16_to_fp (i32
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(zextloadi16 (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
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ro_Wextend16:$extend))))),
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(FCVTSHr (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend))>;
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def : Pat<(f32 (f16_to_fp (i32
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(zextloadi16 (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
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ro_Xextend16:$extend))))),
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(FCVTSHr (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend16:$extend))>;
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def : Pat <(f32 (f16_to_fp (i32
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(zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
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(FCVTSHr (LDRHui GPR64sp:$Rn, uimm12s2:$offset))>;
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def : Pat <(f32 (f16_to_fp (i32
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(zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))),
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(FCVTSHr (LDURHi GPR64sp:$Rn, simm9:$offset))>;
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// f16->f64
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def : Pat<(f64 (fextend (f32 (f16_to_fp (i32
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(zextloadi16 (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
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ro_Wextend16:$extend))))))),
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(FCVTDHr (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend))>;
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def : Pat<(f64 (fextend (f32 (f16_to_fp (i32
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(zextloadi16 (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
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ro_Xextend16:$extend))))))),
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(FCVTDHr (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend16:$extend))>;
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def : Pat <(f64 (fextend (f32 (f16_to_fp (i32
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(zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))))),
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(FCVTDHr (LDRHui GPR64sp:$Rn, uimm12s2:$offset))>;
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def : Pat <(f64 (fextend (f32 (f16_to_fp (i32
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(zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))))),
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(FCVTDHr (LDURHi GPR64sp:$Rn, simm9:$offset))>;
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// When converting to f16 going directly to a store, make sure we use the
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// appropriate direct conversion instructions and store via the FPR16
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// registers rather than going through the GPRs.
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let AddedComplexity = 10 in {
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// f32->f16
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def : Pat< (truncstorei16 (assertzext (i32 (fp_to_f16 FPR32:$Rt))),
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(ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
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ro_Wextend16:$extend)),
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(STRHroW (FCVTHSr FPR32:$Rt), GPR64sp:$Rn, GPR32:$Rm,
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ro_Wextend16:$extend)>;
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def : Pat< (truncstorei16 (assertzext (i32 (fp_to_f16 FPR32:$Rt))),
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(ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
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ro_Xextend16:$extend)),
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(STRHroX (FCVTHSr FPR32:$Rt), GPR64sp:$Rn, GPR64:$Rm,
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ro_Xextend16:$extend)>;
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def : Pat <(truncstorei16 (assertzext (i32 (fp_to_f16 FPR32:$Rt))),
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(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)),
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(STRHui (FCVTHSr FPR32:$Rt), GPR64sp:$Rn, uimm12s2:$offset)>;
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def : Pat <(truncstorei16 (assertzext (i32 (fp_to_f16 FPR32:$Rt))),
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(am_unscaled16 GPR64sp:$Rn, simm9:$offset)),
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(STURHi (FCVTHSr FPR32:$Rt), GPR64sp:$Rn, simm9:$offset)>;
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// f64->f16
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def : Pat< (truncstorei16 (assertzext (i32 (fp_to_f16 (f32 (fround FPR64:$Rt))))),
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(ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
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ro_Wextend16:$extend)),
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(STRHroW (FCVTHDr FPR64:$Rt), GPR64sp:$Rn, GPR32:$Rm,
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ro_Wextend16:$extend)>;
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def : Pat< (truncstorei16 (assertzext (i32 (fp_to_f16 (f32 (fround FPR64:$Rt))))),
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(ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
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ro_Xextend16:$extend)),
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(STRHroX (FCVTHDr FPR64:$Rt), GPR64sp:$Rn, GPR64:$Rm,
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ro_Xextend16:$extend)>;
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def : Pat <(truncstorei16 (assertzext (i32 (fp_to_f16 (f32 (fround FPR64:$Rt))))),
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(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)),
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(STRHui (FCVTHDr FPR64:$Rt), GPR64sp:$Rn, uimm12s2:$offset)>;
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def : Pat <(truncstorei16 (assertzext (i32 (fp_to_f16 (f32 (fround FPR64:$Rt))))),
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(am_unscaled16 GPR64sp:$Rn, simm9:$offset)),
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(STURHi (FCVTHDr FPR64:$Rt), GPR64sp:$Rn, simm9:$offset)>;
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}
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//===----------------------------------------------------------------------===//
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// Floating point single operand instructions.
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//===----------------------------------------------------------------------===//
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@ -18,8 +18,7 @@ define double @load1(i16* nocapture readonly %a) nounwind {
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; CHECK-NEXT: ret
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%tmp = load i16* %a, align 2
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%tmp1 = tail call float @llvm.convert.from.fp16.f32(i16 %tmp)
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%conv = fpext float %tmp1 to double
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%conv = tail call double @llvm.convert.from.fp16.f64(i16 %tmp)
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ret double %conv
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}
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@ -45,8 +44,7 @@ define double @load3(i16* nocapture readonly %a, i32 %i) nounwind {
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%idxprom = sext i32 %i to i64
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%arrayidx = getelementptr inbounds i16* %a, i64 %idxprom
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%tmp = load i16* %arrayidx, align 2
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%tmp1 = tail call float @llvm.convert.from.fp16.f32(i16 %tmp)
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%conv = fpext float %tmp1 to double
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%conv = tail call double @llvm.convert.from.fp16.f64(i16 %tmp)
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ret double %conv
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}
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@ -70,8 +68,7 @@ define double @load5(i16* nocapture readonly %a, i64 %i) nounwind {
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%arrayidx = getelementptr inbounds i16* %a, i64 %i
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%tmp = load i16* %arrayidx, align 2
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%tmp1 = tail call float @llvm.convert.from.fp16.f32(i16 %tmp)
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%conv = fpext float %tmp1 to double
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%conv = tail call double @llvm.convert.from.fp16.f64(i16 %tmp)
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ret double %conv
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}
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@ -95,8 +92,7 @@ define double @load7(i16* nocapture readonly %a) nounwind {
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%arrayidx = getelementptr inbounds i16* %a, i64 10
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%tmp = load i16* %arrayidx, align 2
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%tmp1 = tail call float @llvm.convert.from.fp16.f32(i16 %tmp)
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%conv = fpext float %tmp1 to double
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%conv = tail call double @llvm.convert.from.fp16.f64(i16 %tmp)
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ret double %conv
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}
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@ -120,8 +116,7 @@ define double @load9(i16* nocapture readonly %a) nounwind {
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%arrayidx = getelementptr inbounds i16* %a, i64 -10
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%tmp = load i16* %arrayidx, align 2
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%tmp1 = tail call float @llvm.convert.from.fp16.f32(i16 %tmp)
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%conv = fpext float %tmp1 to double
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%conv = tail call double @llvm.convert.from.fp16.f64(i16 %tmp)
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ret double %conv
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}
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@ -252,3 +247,5 @@ define void @store9(i16* nocapture %a, double %val) nounwind {
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declare i16 @llvm.convert.to.fp16.f32(float) nounwind readnone
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declare float @llvm.convert.from.fp16.f32(i16) nounwind readnone
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declare i16 @llvm.convert.to.fp16.f64(double) nounwind readnone
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declare double @llvm.convert.from.fp16.f64(i16) nounwind readnone
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