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Revert "r226071 - [RegisterCoalescer] Remove copies to reserved registers"
Reverting this while I investigate some bad behavior this is causing. As a possibly-related issue, adding -verify-machineinstrs to one of the test cases now fails because of this change: llc test/CodeGen/X86/2009-02-12-DebugInfoVLA.ll -march=x86-64 -o - -verify-machineinstrs *** Bad machine code: No instruction at def index *** - function: foo - basic block: BB#0 return (0x10007e21f10) [0B;736B) - liverange: [128r,128d:9)[160r,160d:8)[176r,176d:7)[336r,336d:6)[464r,464d:5)[480r,480d:4)[624r,624d:3)[752r,752d:2)[768r,768d:1)[78 4r,784d:0) 0@784r 1@768r 2@752r 3@624r 4@480r 5@464r 6@336r 7@176r 8@160r 9@128r - register: %DS Valno #3 is defined at 624r *** Bad machine code: Live segment doesn't end at a valid instruction *** - function: foo - basic block: BB#0 return (0x10007e21f10) [0B;736B) - liverange: [128r,128d:9)[160r,160d:8)[176r,176d:7)[336r,336d:6)[464r,464d:5)[480r,480d:4)[624r,624d:3)[752r,752d:2)[768r,768d:1)[78 4r,784d:0) 0@784r 1@768r 2@752r 3@624r 4@480r 5@464r 6@336r 7@176r 8@160r 9@128r - register: %DS [624r,624d:3) LLVM ERROR: Found 2 machine code errors. where 624r corresponds exactly to the interval combining change: 624B %RSP<def> = COPY %vreg16; GR64:%vreg16 Considering merging %vreg16 with %RSP RHS = %vreg16 [608r,624r:0) 0@608r updated: 608B %RSP<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%saved_stack.1] Success: %vreg16 -> %RSP Result = %RSP git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226086 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -1,4 +1,4 @@
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; RUN: llc -mcpu=generic -mtriple=arm-eabi < %s | FileCheck %s
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; RUN: llc -mtriple=arm-eabi %s -o /dev/null
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%struct.comment = type { i8**, i32*, i32, i8* }
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%struct.info = type { i32, i32, i32, i32, i32, i32, i32, i8* }
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@@ -7,18 +7,6 @@
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@str215 = external global [2 x i8]
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define void @t1(%struct.state* %v) {
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; Make sure we generate:
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; sub sp, sp, r1
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; instead of:
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; sub r1, sp, r1
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; mov sp, r1
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; CHECK-LABEL: @t1
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; CHECK: bic [[REG1:r[0-9]+]],
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; CHECK-NOT: sub r{{[0-9]+}}, sp, [[REG1]]
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; CHECK: sub sp, sp, [[REG1]]
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%tmp6 = load i32* null
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%tmp8 = alloca float, i32 %tmp6
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store i32 1, i32* null
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