From f934d159ae6b57f05d8163265b9deaa29315d2e7 Mon Sep 17 00:00:00 2001 From: Akira Hatanaka Date: Sat, 15 Sep 2012 01:02:03 +0000 Subject: [PATCH] Handled unaligned load/stores properly in Mips16 Patch by Reed Kotler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163956 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsISelLowering.cpp | 9 +++++++-- test/CodeGen/Mips/ul1.ll | 15 +++++++++++++++ 2 files changed, 22 insertions(+), 2 deletions(-) create mode 100644 test/CodeGen/Mips/ul1.ll diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp index 46c2d6a74ee..871a654609d 100644 --- a/lib/Target/Mips/MipsISelLowering.cpp +++ b/lib/Target/Mips/MipsISelLowering.cpp @@ -161,8 +161,10 @@ MipsTargetLowering(MipsTargetMachine &TM) setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom); setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); - setOperationAction(ISD::LOAD, MVT::i32, Custom); - setOperationAction(ISD::STORE, MVT::i32, Custom); + if (!Subtarget->inMips16Mode()) { + setOperationAction(ISD::LOAD, MVT::i32, Custom); + setOperationAction(ISD::STORE, MVT::i32, Custom); + } if (!TM.Options.NoNaNsFPMath) { setOperationAction(ISD::FABS, MVT::f32, Custom); @@ -309,6 +311,9 @@ MipsTargetLowering(MipsTargetMachine &TM) bool MipsTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const { MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy; + if (Subtarget->inMips16Mode()) + return false; + switch (SVT) { case MVT::i64: case MVT::i32: diff --git a/test/CodeGen/Mips/ul1.ll b/test/CodeGen/Mips/ul1.ll new file mode 100644 index 00000000000..7e64ff4d90f --- /dev/null +++ b/test/CodeGen/Mips/ul1.ll @@ -0,0 +1,15 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +%struct.ua = type <{ i16, i32 }> + +@foo = common global %struct.ua zeroinitializer, align 1 + +define i32 @main() nounwind { +entry: + store i32 10, i32* getelementptr inbounds (%struct.ua* @foo, i32 0, i32 1), align 1 +; 16: sb ${{[0-9]+}}, {{[0-9]+}}(${{[0-9]+}}) +; 16: sb ${{[0-9]+}}, {{[0-9]+}}(${{[0-9]+}}) +; 16: sb ${{[0-9]+}}, {{[0-9]+}}(${{[0-9]+}}) +; 16: sb ${{[0-9]+}}, {{[0-9]+}}(${{[0-9]+}}) + ret i32 0 +} +