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[mips] Fix assertion on i128 addition/subtraction on MIPS64
Summary: In addition to the included tests, this fixes test/CodeGen/Generic/i128-addsub.ll on a mips64 host. Reviewers: atanasyan, sagar, vmedic Reviewed By: vmedic Subscribers: sdkie, llvm-commits Differential Revision: http://reviews.llvm.org/D6610 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227003 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders
95
test/CodeGen/Mips/llvm-ir/add.ll
Normal file
95
test/CodeGen/Mips/llvm-ir/add.ll
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@@ -0,0 +1,95 @@
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; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=ALL-32BIT -check-prefix=M2
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; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=ALL-32BIT -check-prefix=32R1-R2 -check-prefix=32R1
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; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=ALL-32BIT -check-prefix=32R1-R2 -check-prefix=32R2
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; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=ALL-32BIT -check-prefix=32R6
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; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=ALL-64BIT -check-prefix=M4
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; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=ALL-64BIT -check-prefix=64R1-R2
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; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=ALL-64BIT -check-prefix=64R1-R2
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; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=ALL-64BIT -check-prefix=64R6
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; FIXME: We should be able to have signext on the return value without incurring
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; a sign extend.
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define i8 @add_i8(i8 signext %a, i8 signext %b) {
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entry:
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; ALL-LABEL: add_i8:
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; ALL: addu $2, $4, $5
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%r = add i8 %a, %b
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ret i8 %r
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}
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; FIXME: We should be able to have signext on the return value without incurring
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; a sign extend.
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define i16 @add_i16(i16 signext %a, i16 signext %b) {
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entry:
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; ALL-LABEL: add_i16:
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; ALL: addu $2, $4, $5
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%r = add i16 %a, %b
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ret i16 %r
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}
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define signext i32 @add_i32(i32 signext %a, i32 signext %b) {
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entry:
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; ALL-LABEL: add_i32:
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; ALL: addu $2, $4, $5
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%r = add i32 %a, %b
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ret i32 %r
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}
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define signext i64 @add_i64(i64 signext %a, i64 signext %b) {
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entry:
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; ALL-LABEL: add_i64:
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; ALL-32BIT-DAG: addu [[R1:\$3]], $5, $7
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; ALL-32BIT-DAG: sltu [[T0:\$[0-9]+]], [[R1]], $7
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; ALL-32BIT-DAG: addu [[T1:\$[0-9]+]], [[T0]], $6
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; ALL-32BIT-DAG: addu $2, $4, [[T1]]
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; ALL-64BIT: daddu $2, $4, $5
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%r = add i64 %a, %b
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ret i64 %r
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}
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define signext i128 @add_i128(i128 signext %a, i128 signext %b) {
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entry:
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; ALL-LABEL: add_i128:
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; ALL-32BIT-DAG: lw [[A3:\$[0-9]+]], 28($sp)
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; ALL-32BIT-DAG: addu [[T0:\$[0-9]+]], $7, [[A3]]
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; ALL-32BIT-DAG: sltu [[T1:\$[0-9]+]], [[T0]], [[A3]]
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; ALL-32BIT-DAG: lw [[A2:\$[0-9]+]], 24($sp)
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; ALL-32BIT-DAG: addu [[T2:\$[0-9]+]], [[T1]], [[A2]]
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; ALL-32BIT-DAG: addu [[T3:\$[0-9]+]], $6, [[T2]]
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; ALL-32BIT-DAG: sltu [[T4:\$[0-9]+]], [[T3]], [[A2]]
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; ALL-32BIT-DAG: lw [[A1:\$[0-9]+]], 20($sp)
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; ALL-32BIT-DAG: addu [[T5:\$[0-9]+]], [[T4]], [[A1]]
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; ALL-32BIT-DAG: lw [[A0:\$[0-9]+]], 16($sp)
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; ALL-32BIT-DAG: addu [[R1:\$3]], [[R3:\$5]], [[T5]]
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; ALL-32BIT-DAG: sltu [[T6:\$[0-9]+]], [[R1]], [[A1]]
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; ALL-32BIT-DAG: addu [[T7:\$[0-9]+]], [[T6]], [[A0]]
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; ALL-32BIT-DAG: addu $2, [[R2:\$4]], [[T7]]
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; ALL-32BIT-DAG: move [[R2]], [[T3]]
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; ALL-32BIT-DAG: move [[R3]], [[T0]]
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; ALL-64BIT-DAG: daddu [[R0:\$3]], $5, $7
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; ALL-64BIT-DAG: sltu [[T1:\$[0-9]+]], [[R0]], $7
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; ALL-64BIT-DAG: daddu [[T2:\$[0-9]+]], [[T1]], $6
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; ALL-64BIT-DAG: daddu $2, $4, [[T2]]
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%r = add i128 %a, %b
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ret i128 %r
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}
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94
test/CodeGen/Mips/llvm-ir/sub.ll
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94
test/CodeGen/Mips/llvm-ir/sub.ll
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@@ -0,0 +1,94 @@
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; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=ALL-32BIT -check-prefix=M2
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; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=ALL-32BIT -check-prefix=32R1-R2 -check-prefix=32R1
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; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=ALL-32BIT -check-prefix=32R1-R2 -check-prefix=32R2
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; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=ALL-32BIT -check-prefix=32R6
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; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=ALL-64BIT -check-prefix=M4
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; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=ALL-64BIT -check-prefix=64R1-R2
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; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=ALL-64BIT -check-prefix=64R1-R2
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; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=ALL-64BIT -check-prefix=64R6
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; FIXME: We should be able to have signext on the return value without incurring
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; a sign extend.
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define i8 @sub_i8(i8 signext %a, i8 signext %b) {
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entry:
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; ALL-LABEL: sub_i8:
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; ALL: subu $2, $4, $5
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%r = sub i8 %a, %b
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ret i8 %r
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}
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; FIXME: We should be able to have signext on the return value without incurring
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; a sign extend.
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define i16 @sub_i16(i16 signext %a, i16 signext %b) {
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entry:
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; ALL-LABEL: sub_i16:
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; ALL: subu $2, $4, $5
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%r = sub i16 %a, %b
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ret i16 %r
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}
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define signext i32 @sub_i32(i32 signext %a, i32 signext %b) {
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entry:
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; ALL-LABEL: sub_i32:
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; ALL: subu $2, $4, $5
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%r = sub i32 %a, %b
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ret i32 %r
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}
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define signext i64 @sub_i64(i64 signext %a, i64 signext %b) {
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entry:
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; ALL-LABEL: sub_i64:
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; ALL-32BIT-DAG: subu [[R1:\$3]], $5, $7
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; ALL-32BIT-DAG: sltu [[T0:\$[0-9]+]], $5, $7
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; ALL-32BIT-DAG: addu [[T1:\$[0-9]+]], [[T0]], $6
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; ALL-32BIT-DAG: subu $2, $4, [[T1]]
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; ALL-64BIT: dsubu $2, $4, $5
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%r = sub i64 %a, %b
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ret i64 %r
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}
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define signext i128 @sub_i128(i128 signext %a, i128 signext %b) {
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entry:
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; ALL-LABEL: sub_i128:
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; ALL-32BIT-DAG: lw [[A1:\$[0-9]+]], 20($sp)
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; ALL-32BIT-DAG: sltu [[T0:\$[0-9]+]], $5, [[A1]]
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; ALL-32BIT-DAG: lw [[A0:\$[0-9]+]], 16($sp)
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; ALL-32BIT-DAG: addu [[T1:\$[0-9]+]], [[T0]], [[A0]]
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; ALL-32BIT-DAG: lw [[A2:\$[0-9]+]], 24($sp)
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; ALL-32BIT-DAG: lw [[A3:\$[0-9]+]], 28($sp)
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; ALL-32BIT-DAG: subu [[T2:\$[0-9]+]], $7, [[A3]]
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; ALL-32BIT-DAG: subu $2, $4, [[T1]]
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; ALL-32BIT-DAG: sltu [[T3:\$[0-9]+]], $6, [[A2]]
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; ALL-32BIT-DAG: addu [[T4:\$[0-9]+]], [[T3]], [[A1]]
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; ALL-32BIT-DAG: subu $3, $5, [[T4]]
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; ALL-32BIT-DAG: sltu [[T5:\$[0-9]+]], $7, [[A3]]
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; ALL-32BIT-DAG: addu [[T6:\$[0-9]+]], [[T5]], [[A2]]
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; ALL-32BIT-DAG: subu $4, $6, [[T6]]
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; ALL-32BIT-DAG: move $5, [[T2]]
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; ALL-64BIT-DAG: dsubu $3, $5, $7
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; ALL-64BIT-DAG: sltu [[T1:\$[0-9]+]], $5, $7
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; ALL-64BIT-DAG: daddu [[T2:\$[0-9]+]], [[T1]], $6
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; ALL-64BIT-DAG: dsubu $2, $4, [[T2]]
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%r = sub i128 %a, %b
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ret i128 %r
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}
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