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Avoid CSE of instructions which define physical registers across MBBs unless
the physical registers are not allocatable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147902 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -87,6 +87,7 @@ namespace {
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SmallVector<unsigned,2> &PhysDefs) const;
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bool PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
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SmallSet<unsigned,8> &PhysRefs,
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SmallVector<unsigned,2> &PhysDefs,
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bool &NonLocal) const;
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bool isCSECandidate(MachineInstr *MI);
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bool isProfitableToCSE(unsigned CSReg, unsigned Reg,
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@ -222,6 +223,7 @@ bool MachineCSE::hasLivePhysRegDefUses(const MachineInstr *MI,
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bool MachineCSE::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
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SmallSet<unsigned,8> &PhysRefs,
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SmallVector<unsigned,2> &PhysDefs,
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bool &NonLocal) const {
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// For now conservatively returns false if the common subexpression is
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// not in the same basic block as the given instruction. The only exception
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@ -231,10 +233,16 @@ bool MachineCSE::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
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bool CrossMBB = false;
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if (CSMBB != MBB) {
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if (MBB->pred_size() == 1 && *MBB->pred_begin() == CSMBB)
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CrossMBB = true;
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else
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if (MBB->pred_size() != 1 || *MBB->pred_begin() != CSMBB)
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return false;
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for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i) {
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if (TRI->isInAllocatableClass(PhysDefs[i]))
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// Avoid extending live range of physical registers unless
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// they are unallocatable.
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return false;
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}
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CrossMBB = true;
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}
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MachineBasicBlock::const_iterator I = CSMI; I = llvm::next(I);
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MachineBasicBlock::const_iterator E = MI;
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@ -429,7 +437,7 @@ bool MachineCSE::ProcessBlock(MachineBasicBlock *MBB) {
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// in between and the physical register uses were not clobbered.
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unsigned CSVN = VNT.lookup(MI);
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MachineInstr *CSMI = Exps[CSVN];
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if (PhysRegDefsReach(CSMI, MI, PhysRefs, CrossMBBPhysDef))
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if (PhysRegDefsReach(CSMI, MI, PhysRefs, PhysDefs, CrossMBBPhysDef))
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FoundCSE = true;
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}
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