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Avoid CSE of instructions which define physical registers across MBBs unless

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the physical registers are not allocatable.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147902 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2012-01-11 00:38:11 +00:00
parent 37b94c6b4e
commit f96703e62f
1 changed files with 12 additions and 4 deletions
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16
lib/CodeGen/MachineCSE.cpp
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@ -87,6 +87,7 @@ namespace {
SmallVector<unsigned,2> &PhysDefs) const; SmallVector<unsigned,2> &PhysDefs) const;
bool PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI, bool PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
SmallSet<unsigned,8> &PhysRefs, SmallSet<unsigned,8> &PhysRefs,
SmallVector<unsigned,2> &PhysDefs,
bool &NonLocal) const; bool &NonLocal) const;
bool isCSECandidate(MachineInstr *MI); bool isCSECandidate(MachineInstr *MI);
bool isProfitableToCSE(unsigned CSReg, unsigned Reg, bool isProfitableToCSE(unsigned CSReg, unsigned Reg,
@ -222,6 +223,7 @@ bool MachineCSE::hasLivePhysRegDefUses(const MachineInstr *MI,
bool MachineCSE::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI, bool MachineCSE::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
SmallSet<unsigned,8> &PhysRefs, SmallSet<unsigned,8> &PhysRefs,
SmallVector<unsigned,2> &PhysDefs,
bool &NonLocal) const { bool &NonLocal) const {
// For now conservatively returns false if the common subexpression is // For now conservatively returns false if the common subexpression is
// not in the same basic block as the given instruction. The only exception // not in the same basic block as the given instruction. The only exception
@ -231,10 +233,16 @@ bool MachineCSE::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
bool CrossMBB = false; bool CrossMBB = false;
if (CSMBB != MBB) { if (CSMBB != MBB) {
if (MBB->pred_size() == 1 && *MBB->pred_begin() == CSMBB) if (MBB->pred_size() != 1 || *MBB->pred_begin() != CSMBB)
CrossMBB = true;
else
return false; return false;
for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i) {
if (TRI->isInAllocatableClass(PhysDefs[i]))
// Avoid extending live range of physical registers unless
// they are unallocatable.
return false;
}
CrossMBB = true;
} }
MachineBasicBlock::const_iterator I = CSMI; I = llvm::next(I); MachineBasicBlock::const_iterator I = CSMI; I = llvm::next(I);
MachineBasicBlock::const_iterator E = MI; MachineBasicBlock::const_iterator E = MI;
@ -429,7 +437,7 @@ bool MachineCSE::ProcessBlock(MachineBasicBlock *MBB) {
// in between and the physical register uses were not clobbered. // in between and the physical register uses were not clobbered.
unsigned CSVN = VNT.lookup(MI); unsigned CSVN = VNT.lookup(MI);
MachineInstr *CSMI = Exps[CSVN]; MachineInstr *CSMI = Exps[CSVN];
if (PhysRegDefsReach(CSMI, MI, PhysRefs, CrossMBBPhysDef)) if (PhysRegDefsReach(CSMI, MI, PhysRefs, PhysDefs, CrossMBBPhysDef))
FoundCSE = true; FoundCSE = true;
} }