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https://github.com/c64scene-ar/llvm-6502.git
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Add ret instruction to PTX backend
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114788 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -79,7 +79,15 @@ namespace CallingConv {
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/// X86_ThisCall - Similar to X86_StdCall. Passes first argument in ECX,
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/// others via stack. Callee is responsible for stack cleaning. MSVC uses
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/// this by default for methods in its ABI.
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X86_ThisCall = 70
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X86_ThisCall = 70,
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/// PTX_Kernel - Call to a PTX kernel.
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/// Passes all arguments in parameter space.
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PTX_Kernel = 71,
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/// PTX_Device - Call to a PTX device function.
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/// Passes all arguments in register or parameter space.
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PTX_Device = 72
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};
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} // End CallingConv namespace
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@ -544,6 +544,8 @@ lltok::Kind LLLexer::LexIdentifier() {
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KEYWORD(arm_aapcscc);
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KEYWORD(arm_aapcs_vfpcc);
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KEYWORD(msp430_intrcc);
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KEYWORD(ptx_kernel);
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KEYWORD(ptx_device);
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KEYWORD(cc);
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KEYWORD(c);
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@ -1084,6 +1084,8 @@ bool LLParser::ParseOptionalVisibility(unsigned &Res) {
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/// ::= 'arm_aapcscc'
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/// ::= 'arm_aapcs_vfpcc'
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/// ::= 'msp430_intrcc'
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/// ::= 'ptx_kernel'
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/// ::= 'ptx_device'
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/// ::= 'cc' UINT
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///
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bool LLParser::ParseOptionalCallingConv(CallingConv::ID &CC) {
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@ -1099,6 +1101,8 @@ bool LLParser::ParseOptionalCallingConv(CallingConv::ID &CC) {
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case lltok::kw_arm_aapcscc: CC = CallingConv::ARM_AAPCS; break;
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case lltok::kw_arm_aapcs_vfpcc:CC = CallingConv::ARM_AAPCS_VFP; break;
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case lltok::kw_msp430_intrcc: CC = CallingConv::MSP430_INTR; break;
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case lltok::kw_ptx_kernel: CC = CallingConv::PTX_Kernel; break;
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case lltok::kw_ptx_device: CC = CallingConv::PTX_Device; break;
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case lltok::kw_cc: {
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unsigned ArbitraryCC;
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Lex.Lex();
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@ -72,6 +72,7 @@ namespace lltok {
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kw_x86_stdcallcc, kw_x86_fastcallcc, kw_x86_thiscallcc,
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kw_arm_apcscc, kw_arm_aapcscc, kw_arm_aapcs_vfpcc,
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kw_msp430_intrcc,
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kw_ptx_kernel, kw_ptx_device,
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kw_signext,
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kw_zeroext,
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@ -32,6 +32,7 @@ const char *PTXTargetLowering::getTargetNodeName(unsigned Opcode) const {
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switch (Opcode) {
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default: llvm_unreachable("Unknown opcode");
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case PTXISD::EXIT: return "PTXISD::EXIT";
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case PTXISD::RET: return "PTXISD::RET";
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}
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}
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@ -58,5 +59,25 @@ SDValue PTXTargetLowering::
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const SmallVectorImpl<SDValue> &OutVals,
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DebugLoc dl,
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SelectionDAG &DAG) const {
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return DAG.getNode(PTXISD::EXIT, dl, MVT::Other, Chain);
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assert(!isVarArg && "PTX does not support var args.");
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switch (CallConv) {
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default:
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llvm_unreachable("Unsupported calling convention.");
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case CallingConv::PTX_Kernel:
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assert(Outs.size() == 0 && "Kernel must return void.");
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return DAG.getNode(PTXISD::EXIT, dl, MVT::Other, Chain);
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case CallingConv::PTX_Device:
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assert(Outs.size() <= 1 && "Can at most return one value.");
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break;
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}
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// PTX_Device
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if (Outs.size() == 0)
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return DAG.getNode(PTXISD::RET, dl, MVT::Other, Chain);
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// TODO: allocate return register
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SDValue Flag;
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return DAG.getNode(PTXISD::RET, dl, MVT::Other, Chain, Flag);
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}
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@ -24,7 +24,8 @@ class PTXTargetMachine;
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namespace PTXISD {
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enum NodeType {
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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EXIT
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EXIT,
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RET
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};
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} // namespace PTXISD
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@ -23,6 +23,8 @@ include "PTXInstrFormats.td"
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def PTXexit
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: SDNode<"PTXISD::EXIT", SDTNone, [SDNPHasChain]>;
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def PTXret
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: SDNode<"PTXISD::RET", SDTNone, [SDNPHasChain]>;
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//===----------------------------------------------------------------------===//
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// Instructions
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@ -30,4 +32,5 @@ def PTXexit
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let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
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def EXIT : InstPTX<(outs), (ins), "exit", [(PTXexit)]>;
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def RET : InstPTX<(outs), (ins), "ret", [(PTXret)]>;
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}
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@ -1579,6 +1579,8 @@ void AssemblyWriter::printFunction(const Function *F) {
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case CallingConv::ARM_AAPCS: Out << "arm_aapcscc "; break;
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case CallingConv::ARM_AAPCS_VFP:Out << "arm_aapcs_vfpcc "; break;
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case CallingConv::MSP430_INTR: Out << "msp430_intrcc "; break;
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case CallingConv::PTX_Kernel: Out << "ptx_kernel"; break;
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case CallingConv::PTX_Device: Out << "ptx_device"; break;
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default: Out << "cc" << F->getCallingConv() << " "; break;
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}
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@ -1847,6 +1849,8 @@ void AssemblyWriter::printInstruction(const Instruction &I) {
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case CallingConv::ARM_AAPCS: Out << " arm_aapcscc "; break;
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case CallingConv::ARM_AAPCS_VFP:Out << " arm_aapcs_vfpcc "; break;
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case CallingConv::MSP430_INTR: Out << " msp430_intrcc "; break;
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case CallingConv::PTX_Kernel: Out << " ptx_kernel"; break;
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case CallingConv::PTX_Device: Out << " ptx_device"; break;
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default: Out << " cc" << CI->getCallingConv(); break;
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}
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@ -1901,6 +1905,8 @@ void AssemblyWriter::printInstruction(const Instruction &I) {
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case CallingConv::ARM_AAPCS: Out << " arm_aapcscc "; break;
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case CallingConv::ARM_AAPCS_VFP:Out << " arm_aapcs_vfpcc "; break;
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case CallingConv::MSP430_INTR: Out << " msp430_intrcc "; break;
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case CallingConv::PTX_Kernel: Out << " ptx_kernel"; break;
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case CallingConv::PTX_Device: Out << " ptx_device"; break;
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default: Out << " cc" << II->getCallingConv(); break;
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}
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@ -685,6 +685,8 @@ void Verifier::visitFunction(Function &F) {
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case CallingConv::Cold:
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case CallingConv::X86_FastCall:
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case CallingConv::X86_ThisCall:
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case CallingConv::PTX_Kernel:
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case CallingConv::PTX_Device:
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Assert1(!F.isVarArg(),
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"Varargs functions must have C calling conventions!", &F);
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break;
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@ -1,6 +1,6 @@
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; RUN: llc < %s -march=ptx | FileCheck %s
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define void @t1() {
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define ptx_kernel void @t1() {
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;CHECK: exit;
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ret void
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}
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@ -49,6 +49,7 @@ syn keyword llvmKeyword hidden protected default
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syn keyword llvmKeyword except deplibs
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syn keyword llvmKeyword volatile fastcc coldcc cc ccc
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syn keyword llvmKeyword x86_stdcallcc x86_fastcallcc
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syn keyword llvmKeyword ptx_kernel ptx_device
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syn keyword llvmKeyword signext zeroext inreg sret nounwind noreturn
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syn keyword llvmKeyword nocapture byval nest readnone readonly noalias
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syn keyword llvmKeyword inlinehint noinline alwaysinline optsize ssp sspreq
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