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Replace sra with srl if a single sign bit is required

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E.g. (and (sra (i32 x) 31) 2) -> (and (srl (i32 x) 30) 2).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192884 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Sandiford 2013-10-17 11:16:57 +00:00
parent 888cbad774
commit f9a5e40b90
3 changed files with 30 additions and 8 deletions
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17
lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -750,13 +750,24 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
// If the input sign bit is known to be zero, or if none of the top bits
// are demanded, turn this into an unsigned shift right.
if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits)
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
Op.getOperand(0),
Op.getOperand(1)));
} else if (KnownOne.intersects(SignBit)) { // New bits are known one.
KnownOne |= HighBits;
int Log2 = NewMask.exactLogBase2();
if (Log2 >= 0) {
// The bit must come from the sign.
SDValue NewSA =
TLO.DAG.getConstant(BitWidth - 1 - Log2,
Op.getOperand(1).getValueType());
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
Op.getOperand(0), NewSA));
}
if (KnownOne.intersects(SignBit))
// New bits are known one.
KnownOne |= HighBits;
}
break;
case ISD::SIGN_EXTEND_INREG: {

9
test/CodeGen/PowerPC/rlwimi-and.ll
View File

@ -28,12 +28,11 @@ codeRepl17: ; preds = %codeRepl4
store i16 %rvml38.sroa.0.0.insert.insert, i16* undef, align 2
unreachable
; FIXME: the SLWI could be folded into the RLWIMI to give a rotate of 8.
; CHECK: @test
; CHECK-DAG: slwi [[R1:[0-9]+]],
; CHECK-DAG: rlwinm [[R2:[0-9]+]],
; CHECK-DAG: srawi [[R3:[0-9]+]], [[R1]]
; CHECK-DAG: rlwinm [[R4:[0-9]+]], [[R3]], 0, 23, 23
; CHECK: rlwimi [[R4]], [[R2]], 0,
; CHECK-DAG: slwi [[R1:[0-9]+]], {{[0-9]+}}, 31
; CHECK-DAG: rlwinm [[R2:[0-9]+]], {{[0-9]+}}, 0, 31, 31
; CHECK: rlwimi [[R2]], [[R1]], 9, 23, 23
codeRepl29: ; preds = %codeRepl1
unreachable

12
test/CodeGen/SystemZ/shift-10.ll
View File

@ -64,3 +64,15 @@ define i64 @f5(i32 %a) {
%or = or i64 %shl, 7
ret i64 %or
}
; Test that SRA gets replaced with SRL if the sign bit is the only one
; that matters.
define i64 @f6(i64 %a) {
; CHECK-LABEL: f6:
; CHECK: risbg %r2, %r2, 55, 183, 19
; CHECK: br %r14
%shl = shl i64 %a, 10
%shr = ashr i64 %shl, 60
%and = and i64 %shr, 256
ret i64 %and
}