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[mips] Rename class and functions. Simplify code.

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No functionality changes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180897 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
2013-05-01 23:41:31 +00:00
parent 0e1327e4aa
commit f9a5e7e4e9
1 changed files with 28 additions and 25 deletions
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53
lib/Target/Mips/MipsSEFrameLowering.cpp
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@@ -32,17 +32,19 @@ using namespace llvm;
namespace { namespace {
typedef MachineBasicBlock::iterator Iter; typedef MachineBasicBlock::iterator Iter;
/// Helper class to expand accumulator pseudos. /// Helper class to expand pseudos.
class ExpandACCPseudo { class ExpandPseudo {
public: public:
ExpandACCPseudo(MachineFunction &MF); ExpandPseudo(MachineFunction &MF);
bool expand(); bool expand();
private: private:
bool expandInstr(MachineBasicBlock &MBB, Iter I); bool expandInstr(MachineBasicBlock &MBB, Iter I);
void expandLoad(MachineBasicBlock &MBB, Iter I, unsigned RegSize); void expandLoadACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize);
void expandStore(MachineBasicBlock &MBB, Iter I, unsigned RegSize); void expandStoreACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize);
bool expandCopy(MachineBasicBlock &MBB, Iter I); bool expandCopy(MachineBasicBlock &MBB, Iter I);
bool expandCopyACC(MachineBasicBlock &MBB, Iter I, unsigned Dst,
unsigned Src, unsigned RegSize);
MachineFunction &MF; MachineFunction &MF;
const MipsSEInstrInfo &TII; const MipsSEInstrInfo &TII;
@@ -51,12 +53,12 @@ private:
}; };
} }
ExpandACCPseudo::ExpandACCPseudo(MachineFunction &MF_) ExpandPseudo::ExpandPseudo(MachineFunction &MF_)
: MF(MF_), : MF(MF_),
TII(*static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo())), TII(*static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo())),
RegInfo(TII.getRegisterInfo()), MRI(MF.getRegInfo()) {} RegInfo(TII.getRegisterInfo()), MRI(MF.getRegInfo()) {}
bool ExpandACCPseudo::expand() { bool ExpandPseudo::expand() {
bool Expanded = false; bool Expanded = false;
for (MachineFunction::iterator BB = MF.begin(), BBEnd = MF.end(); for (MachineFunction::iterator BB = MF.begin(), BBEnd = MF.end();
@@ -67,27 +69,27 @@ bool ExpandACCPseudo::expand() {
return Expanded; return Expanded;
} }
bool ExpandACCPseudo::expandInstr(MachineBasicBlock &MBB, Iter I) { bool ExpandPseudo::expandInstr(MachineBasicBlock &MBB, Iter I) {
switch(I->getOpcode()) { switch(I->getOpcode()) {
case Mips::LOAD_AC64: case Mips::LOAD_AC64:
case Mips::LOAD_AC64_P8: case Mips::LOAD_AC64_P8:
case Mips::LOAD_AC_DSP: case Mips::LOAD_AC_DSP:
case Mips::LOAD_AC_DSP_P8: case Mips::LOAD_AC_DSP_P8:
expandLoad(MBB, I, 4); expandLoadACC(MBB, I, 4);
break; break;
case Mips::LOAD_AC128: case Mips::LOAD_AC128:
case Mips::LOAD_AC128_P8: case Mips::LOAD_AC128_P8:
expandLoad(MBB, I, 8); expandLoadACC(MBB, I, 8);
break; break;
case Mips::STORE_AC64: case Mips::STORE_AC64:
case Mips::STORE_AC64_P8: case Mips::STORE_AC64_P8:
case Mips::STORE_AC_DSP: case Mips::STORE_AC_DSP:
case Mips::STORE_AC_DSP_P8: case Mips::STORE_AC_DSP_P8:
expandStore(MBB, I, 4); expandStoreACC(MBB, I, 4);
break; break;
case Mips::STORE_AC128: case Mips::STORE_AC128:
case Mips::STORE_AC128_P8: case Mips::STORE_AC128_P8:
expandStore(MBB, I, 8); expandStoreACC(MBB, I, 8);
break; break;
case TargetOpcode::COPY: case TargetOpcode::COPY:
if (!expandCopy(MBB, I)) if (!expandCopy(MBB, I))
@@ -101,7 +103,7 @@ bool ExpandACCPseudo::expandInstr(MachineBasicBlock &MBB, Iter I) {
return true; return true;
} }
void ExpandACCPseudo::expandLoad(MachineBasicBlock &MBB, Iter I, void ExpandPseudo::expandLoadACC(MachineBasicBlock &MBB, Iter I,
unsigned RegSize) { unsigned RegSize) {
// load $vr0, FI // load $vr0, FI
// copy lo, $vr0 // copy lo, $vr0
@@ -125,7 +127,7 @@ void ExpandACCPseudo::expandLoad(MachineBasicBlock &MBB, Iter I,
BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill); BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill);
} }
void ExpandACCPseudo::expandStore(MachineBasicBlock &MBB, Iter I, void ExpandPseudo::expandStoreACC(MachineBasicBlock &MBB, Iter I,
unsigned RegSize) { unsigned RegSize) {
// copy $vr0, lo // copy $vr0, lo
// store $vr0, FI // store $vr0, FI
@@ -149,19 +151,20 @@ void ExpandACCPseudo::expandStore(MachineBasicBlock &MBB, Iter I,
TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize); TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize);
} }
bool ExpandACCPseudo::expandCopy(MachineBasicBlock &MBB, Iter I) { bool ExpandPseudo::expandCopy(MachineBasicBlock &MBB, Iter I) {
unsigned Dst = I->getOperand(0).getReg(), Src = I->getOperand(1).getReg(); unsigned Dst = I->getOperand(0).getReg(), Src = I->getOperand(1).getReg();
unsigned RegSize;
if (Mips::ACRegsDSPRegClass.contains(Dst) && if (Mips::ACRegsDSPRegClass.contains(Dst, Src))
Mips::ACRegsDSPRegClass.contains(Src)) return expandCopyACC(MBB, I, Dst, Src, 4);
RegSize = 4;
else if (Mips::ACRegs128RegClass.contains(Dst) &&
Mips::ACRegs128RegClass.contains(Src))
RegSize = 8;
else
return false;
if (Mips::ACRegs128RegClass.contains(Dst, Src))
return expandCopyACC(MBB, I, Dst, Src, 8);
return false;
}
bool ExpandPseudo::expandCopyACC(MachineBasicBlock &MBB, Iter I, unsigned Dst,
unsigned Src, unsigned RegSize) {
// copy $vr0, src_lo // copy $vr0, src_lo
// copy dst_lo, $vr0 // copy dst_lo, $vr0
// copy $vr1, src_hi // copy $vr1, src_hi
@@ -446,7 +449,7 @@ processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
// Expand pseudo instructions which load, store or copy accumulators. // Expand pseudo instructions which load, store or copy accumulators.
// Add an emergency spill slot if a pseudo was expanded. // Add an emergency spill slot if a pseudo was expanded.
if (ExpandACCPseudo(MF).expand()) { if (ExpandPseudo(MF).expand()) {
// The spill slot should be half the size of the accumulator. If target is // The spill slot should be half the size of the accumulator. If target is
// mips64, it should be 64-bit, otherwise it should be 32-bt. // mips64, it should be 64-bit, otherwise it should be 32-bt.
const TargetRegisterClass *RC = STI.hasMips64() ? const TargetRegisterClass *RC = STI.hasMips64() ?