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remove xchg and shift-reg-by-1 instructions, which are dead.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45870 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2008-01-11 18:00:50 +00:00
parent 047ad94fc0
commit f9b3f37abc
3 changed files with 6 additions and 71 deletions
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16
lib/Target/X86/X86Instr64bit.td
View File

@ -161,17 +161,6 @@ let isTwoAddress = 1 in
def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
"bswap{q}\t$dst",
[(set GR64:$dst, (bswap GR64:$src))]>, TB;
// Exchange
let neverHasSideEffects = 1 in {
def XCHG64rr : RI<0x87, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
"xchg{q}\t{$src2|$src1}, {$src1|$src2}", []>;
let mayLoad = 1, mayStore = 1 in {
def XCHG64mr : RI<0x87, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
"xchg{q}\t{$src2|$src1}, {$src1|$src2}", []>;
def XCHG64rm : RI<0x87, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
"xchg{q}\t{$src2|$src1}, {$src1|$src2}", []>;
}
}
// Bit scan instructions.
let Defs = [EFLAGS] in {
@ -526,9 +515,8 @@ let isConvertibleToThreeAddress = 1 in // Can transform into LEA.
def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
"shl{q}\t{$src2, $dst|$dst, $src2}",
[(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>;
let neverHasSideEffects = 1 in
def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
"shl{q}\t$dst", []>;
// NOTE: We don't use shifts of a register by one, because 'add reg,reg' is
// cheaper.
} // isTwoAddress
let Uses = [CL] in

16
lib/Target/X86/X86InstrInfo.cpp
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@ -145,16 +145,12 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
{ X86::SBB64ri32, X86::SBB64mi32 },
{ X86::SBB64ri8, X86::SBB64mi8 },
{ X86::SBB64rr, X86::SBB64mr },
{ X86::SHL16r1, X86::SHL16m1 },
{ X86::SHL16rCL, X86::SHL16mCL },
{ X86::SHL16ri, X86::SHL16mi },
{ X86::SHL32r1, X86::SHL32m1 },
{ X86::SHL32rCL, X86::SHL32mCL },
{ X86::SHL32ri, X86::SHL32mi },
{ X86::SHL64r1, X86::SHL64m1 },
{ X86::SHL64rCL, X86::SHL64mCL },
{ X86::SHL64ri, X86::SHL64mi },
{ X86::SHL8r1, X86::SHL8m1 },
{ X86::SHL8rCL, X86::SHL8mCL },
{ X86::SHL8ri, X86::SHL8mi },
{ X86::SHLD16rrCL, X86::SHLD16mrCL },
@ -286,11 +282,7 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
{ X86::TEST16ri, X86::TEST16mi, 1 },
{ X86::TEST32ri, X86::TEST32mi, 1 },
{ X86::TEST64ri32, X86::TEST64mi32, 1 },
{ X86::TEST8ri, X86::TEST8mi, 1 },
{ X86::XCHG16rr, X86::XCHG16mr, 0 },
{ X86::XCHG32rr, X86::XCHG32mr, 0 },
{ X86::XCHG64rr, X86::XCHG64mr, 0 },
{ X86::XCHG8rr, X86::XCHG8mr, 0 }
{ X86::TEST8ri, X86::TEST8mi, 1 }
};
for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
@ -417,11 +409,7 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
{ X86::TEST8rr, X86::TEST8rm },
// FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
{ X86::UCOMISDrr, X86::UCOMISDrm },
{ X86::UCOMISSrr, X86::UCOMISSrm },
{ X86::XCHG16rr, X86::XCHG16rm },
{ X86::XCHG32rr, X86::XCHG32rm },
{ X86::XCHG64rr, X86::XCHG64rm },
{ X86::XCHG8rr, X86::XCHG8rm }
{ X86::UCOMISSrr, X86::UCOMISSrm }
};
for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {

45
lib/Target/X86/X86InstrInfo.td
View File

@ -418,39 +418,6 @@ let isTwoAddress = 1 in // GR32 = bswap GR32
"bswap{l}\t$dst",
[(set GR32:$dst, (bswap GR32:$src))]>, TB;
// FIXME: Model xchg* as two address instructions?
let neverHasSideEffects = 1 in {
def XCHG8rr : I<0x86, MRMDestReg, // xchg GR8, GR8
(outs), (ins GR8:$src1, GR8:$src2),
"xchg{b}\t{$src2|$src1}, {$src1|$src2}", []>;
def XCHG16rr : I<0x87, MRMDestReg, // xchg GR16, GR16
(outs), (ins GR16:$src1, GR16:$src2),
"xchg{w}\t{$src2|$src1}, {$src1|$src2}", []>, OpSize;
def XCHG32rr : I<0x87, MRMDestReg, // xchg GR32, GR32
(outs), (ins GR32:$src1, GR32:$src2),
"xchg{l}\t{$src2|$src1}, {$src1|$src2}", []>;
}
let mayLoad = 1, mayStore = 1 in {
def XCHG8mr : I<0x86, MRMDestMem,
(outs), (ins i8mem:$src1, GR8:$src2),
"xchg{b}\t{$src2|$src1}, {$src1|$src2}", []>;
def XCHG16mr : I<0x87, MRMDestMem,
(outs), (ins i16mem:$src1, GR16:$src2),
"xchg{w}\t{$src2|$src1}, {$src1|$src2}", []>, OpSize;
def XCHG32mr : I<0x87, MRMDestMem,
(outs), (ins i32mem:$src1, GR32:$src2),
"xchg{l}\t{$src2|$src1}, {$src1|$src2}", []>;
def XCHG8rm : I<0x86, MRMSrcMem,
(outs), (ins GR8:$src1, i8mem:$src2),
"xchg{b}\t{$src2|$src1}, {$src1|$src2}", []>;
def XCHG16rm : I<0x87, MRMSrcMem,
(outs), (ins GR16:$src1, i16mem:$src2),
"xchg{w}\t{$src2|$src1}, {$src1|$src2}", []>, OpSize;
def XCHG32rm : I<0x87, MRMSrcMem,
(outs), (ins GR32:$src1, i32mem:$src2),
"xchg{l}\t{$src2|$src1}, {$src1|$src2}", []>;
}
// Bit scan instructions.
let Defs = [EFLAGS] in {
@ -1417,16 +1384,8 @@ def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
"shl{l}\t{$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
}
// Shift left by one. Not used because (add x, x) is slightly cheaper.
let neverHasSideEffects = 1 in {
def SHL8r1 : I<0xD0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
"shl{b}\t$dst", []>;
def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
"shl{w}\t$dst", []>, OpSize;
def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
"shl{l}\t$dst", []>;
// NOTE: We don't use shifts of a register by one, because 'add reg,reg' is
// cheaper.
}
let isTwoAddress = 0 in {