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add enough support for indirect branch for the feature test to pass
(assembler,asmprinter, bc reader+writer) and document it. Codegen currently aborts on it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85274 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1001,7 +1001,7 @@ static void WriteInstruction(const Instruction &I, unsigned InstID,
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case Instruction::Br:
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{
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Code = bitc::FUNC_CODE_INST_BR;
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BranchInst &II(cast<BranchInst>(I));
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BranchInst &II = cast<BranchInst>(I);
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Vals.push_back(VE.getValueID(II.getSuccessor(0)));
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if (II.isConditional()) {
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Vals.push_back(VE.getValueID(II.getSuccessor(1)));
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@ -1015,6 +1015,13 @@ static void WriteInstruction(const Instruction &I, unsigned InstID,
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for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i)
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Vals.push_back(VE.getValueID(I.getOperand(i)));
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break;
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case Instruction::IndBr:
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Code = bitc::FUNC_CODE_INST_INDBR;
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Vals.push_back(VE.getTypeID(I.getOperand(0)->getType()));
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for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i)
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Vals.push_back(VE.getValueID(I.getOperand(i)));
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break;
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case Instruction::Invoke: {
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const InvokeInst *II = cast<InvokeInst>(&I);
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const Value *Callee(II->getCalledValue());
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