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Add another permutation where we should get rid of a-a.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61401 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dale Johannesen 2008-12-23 23:01:27 +00:00
parent c7a37d4ff2
commit f9cbc1f9ac
2 changed files with 35 additions and 4 deletions
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15
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -1177,13 +1177,20 @@ SDValue DAGCombiner::visitSUB(SDNode *N) {
return N0.getOperand(1);
// fold (A+B)-B -> A
if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
return N0.getOperand(0);
// fold ((A+(B-C))-B) -> A-C
return N0.getOperand(0);
// fold ((A+(B+-C))-B) -> A+-C
if (N0.getOpcode() == ISD::ADD &&
N0.getOperand(1).getOpcode() == ISD::SUB &&
(N0.getOperand(1).getOpcode() == ISD::SUB ||
N0.getOperand(1).getOpcode() == ISD::ADD) &&
N0.getOperand(1).getOperand(0) == N1)
return DAG.getNode(ISD::SUB, VT, N0.getOperand(0),
return DAG.getNode(N0.getOperand(1).getOpcode(), VT, N0.getOperand(0),
N0.getOperand(1).getOperand(1));
// fold ((A+(C+B))-B) -> A+C
if (N0.getOpcode() == ISD::ADD &&
N0.getOperand(1).getOpcode() == ISD::ADD &&
N0.getOperand(1).getOperand(1) == N1)
return DAG.getNode(ISD::ADD, VT, N0.getOperand(0),
N0.getOperand(1).getOperand(0));
// fold ((A-(B-C))-C) -> A-B
if (N0.getOpcode() == ISD::SUB &&
N0.getOperand(1).getOpcode() == ISD::SUB &&

24
test/CodeGen/X86/2008-12-23-dagcombine-6.ll Normal file
View File

@ -0,0 +1,24 @@
; RUN: llvm-as < %s | llc -march=x86 | grep "(%esp)" | count 4
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i386-apple-darwin9.5"
; a - a should be found and removed, leaving refs to only L and P
define i32 @test(i32 %a, i32 %L, i32 %P) nounwind {
entry:
%0 = add i32 %a, %L
%1 = add i32 %P, %0
%2 = sub i32 %1, %a
br label %return
return: ; preds = %bb3
ret i32 %2
}
define i32 @test2(i32 %a, i32 %L, i32 %P) nounwind {
entry:
%0 = add i32 %L, %a
%1 = add i32 %P, %0
%2 = sub i32 %1, %a
br label %return
return: ; preds = %bb3
ret i32 %2
}