mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-11-03 14:21:30 +00:00
Start trying to print instructions more correctly. For now we also print out the opcode for each instruction as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4743 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
@@ -67,10 +67,99 @@ bool Printer::runOnFunction (Function & F)
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return false;
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return false;
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}
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}
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static void printOp(std::ostream &O, const MachineOperand &MO,
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const MRegisterInfo &RI) {
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switch (MO.getType()) {
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case MachineOperand::MO_VirtualRegister:
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if (MO.getReg() < MRegisterInfo::FirstVirtualRegister)
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O << RI.get(MO.getReg()).Name;
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else
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O << "%reg" << MO.getReg();
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return;
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default:
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O << "<unknown op ty>"; return;
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}
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}
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static inline void toHexDigit(std::ostream &O, unsigned char V) {
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if (V >= 10)
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O << (char)('A'+V-10);
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else
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O << (char)('0'+V);
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}
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static std::ostream &toHex(std::ostream &O, unsigned char V) {
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toHexDigit(O, V >> 4);
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toHexDigit(O, V & 0xF);
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return O;
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}
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// print - Print out an x86 instruction in intel syntax
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// print - Print out an x86 instruction in intel syntax
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void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
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void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
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const TargetMachine &TM) const {
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const TargetMachine &TM) const {
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// FIXME: This sucks.
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unsigned Opcode = MI->getOpcode();
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O << getName(MI->getOpCode()) << "\n";
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const MachineInstrDescriptor &Desc = get(Opcode);
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if (Desc.TSFlags & X86II::TB)
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O << "0F ";
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switch (Desc.TSFlags & X86II::FormMask) {
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case X86II::OtherFrm:
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O << "\t";
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O << "-"; MI->print(O, TM);
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break;
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case X86II::RawFrm:
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toHex(O, getBaseOpcodeFor(Opcode)) << "\t";
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O << getName(MI->getOpCode()) << " ";
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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if (i) O << ", ";
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printOp(O, MI->getOperand(i), RI);
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}
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O << "\n";
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return;
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case X86II::AddRegFrm:
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O << "\t-"; MI->print(O, TM); break;
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case X86II::MRMDestReg:
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// There are two acceptable forms of MRMDestReg instructions, those with 3
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// and 2 operands:
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//
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// 3 Operands: in this form, the first two registers (the destination, and
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// the first operand) should be the same, post register allocation. The 3rd
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// operand is an additional input. This should be for things like add
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// instructions.
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//
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// 2 Operands: this is for things like mov that do not read a second input
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//
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assert(((MI->getNumOperands() == 3 &&
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(MI->getOperand(0).getType()==MachineOperand::MO_VirtualRegister&&
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MI->getOperand(1).getType()==MachineOperand::MO_VirtualRegister))||
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(MI->getNumOperands() == 2 &&
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(MI->getOperand(0).getType()==MachineOperand::MO_VirtualRegister)))
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&& MI->getOperand(MI->getNumOperands()-1).getType() ==
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MachineOperand::MO_VirtualRegister &&
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"Bad format for MRMDestReg!");
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if (MI->getNumOperands() == 3 &&
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MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
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O << "**";
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O << "\t";
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O << getName(MI->getOpCode()) << " ";
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printOp(O, MI->getOperand(0), RI);
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O << ", ";
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printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
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O << "\n";
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return;
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case X86II::MRMDestMem:
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case X86II::MRMSrcReg:
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case X86II::MRMSrcMem:
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default:
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O << "\t-"; MI->print(O, TM); break;
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}
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}
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}
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@@ -67,10 +67,99 @@ bool Printer::runOnFunction (Function & F)
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return false;
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return false;
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}
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}
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static void printOp(std::ostream &O, const MachineOperand &MO,
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const MRegisterInfo &RI) {
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switch (MO.getType()) {
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case MachineOperand::MO_VirtualRegister:
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if (MO.getReg() < MRegisterInfo::FirstVirtualRegister)
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O << RI.get(MO.getReg()).Name;
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else
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O << "%reg" << MO.getReg();
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return;
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default:
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O << "<unknown op ty>"; return;
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}
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}
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static inline void toHexDigit(std::ostream &O, unsigned char V) {
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if (V >= 10)
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O << (char)('A'+V-10);
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else
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O << (char)('0'+V);
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}
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static std::ostream &toHex(std::ostream &O, unsigned char V) {
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toHexDigit(O, V >> 4);
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toHexDigit(O, V & 0xF);
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return O;
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}
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// print - Print out an x86 instruction in intel syntax
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// print - Print out an x86 instruction in intel syntax
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void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
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void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
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const TargetMachine &TM) const {
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const TargetMachine &TM) const {
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// FIXME: This sucks.
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unsigned Opcode = MI->getOpcode();
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O << getName(MI->getOpCode()) << "\n";
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const MachineInstrDescriptor &Desc = get(Opcode);
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if (Desc.TSFlags & X86II::TB)
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O << "0F ";
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switch (Desc.TSFlags & X86II::FormMask) {
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case X86II::OtherFrm:
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O << "\t";
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O << "-"; MI->print(O, TM);
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break;
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case X86II::RawFrm:
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toHex(O, getBaseOpcodeFor(Opcode)) << "\t";
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O << getName(MI->getOpCode()) << " ";
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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if (i) O << ", ";
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printOp(O, MI->getOperand(i), RI);
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}
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O << "\n";
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return;
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case X86II::AddRegFrm:
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O << "\t-"; MI->print(O, TM); break;
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case X86II::MRMDestReg:
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// There are two acceptable forms of MRMDestReg instructions, those with 3
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// and 2 operands:
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//
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// 3 Operands: in this form, the first two registers (the destination, and
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// the first operand) should be the same, post register allocation. The 3rd
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// operand is an additional input. This should be for things like add
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// instructions.
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//
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// 2 Operands: this is for things like mov that do not read a second input
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//
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assert(((MI->getNumOperands() == 3 &&
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(MI->getOperand(0).getType()==MachineOperand::MO_VirtualRegister&&
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MI->getOperand(1).getType()==MachineOperand::MO_VirtualRegister))||
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(MI->getNumOperands() == 2 &&
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(MI->getOperand(0).getType()==MachineOperand::MO_VirtualRegister)))
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&& MI->getOperand(MI->getNumOperands()-1).getType() ==
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MachineOperand::MO_VirtualRegister &&
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"Bad format for MRMDestReg!");
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if (MI->getNumOperands() == 3 &&
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MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
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O << "**";
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O << "\t";
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O << getName(MI->getOpCode()) << " ";
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printOp(O, MI->getOperand(0), RI);
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O << ", ";
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printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
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O << "\n";
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return;
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case X86II::MRMDestMem:
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case X86II::MRMSrcReg:
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case X86II::MRMSrcMem:
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default:
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O << "\t-"; MI->print(O, TM); break;
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}
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}
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}
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