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[ARM64][fast-isel] Fast-isel doesn't know how to handle f128.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207659 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier
2014-04-30 15:29:57 +00:00
parent 3dbcd2e69e
commit fa2e88da1c
2 changed files with 47 additions and 2 deletions
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15
lib/Target/ARM64/ARM64FastISel.cpp
View File

@@ -197,6 +197,9 @@ unsigned ARM64FastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
} }
unsigned ARM64FastISel::ARM64MaterializeFP(const ConstantFP *CFP, MVT VT) { unsigned ARM64FastISel::ARM64MaterializeFP(const ConstantFP *CFP, MVT VT) {
if (VT != MVT::f32 && VT != MVT::f64)
return 0;
const APFloat Val = CFP->getValueAPF(); const APFloat Val = CFP->getValueAPF();
bool is64bit = (VT == MVT::f64); bool is64bit = (VT == MVT::f64);
@@ -418,7 +421,11 @@ bool ARM64FastISel::isTypeLegal(Type *Ty, MVT &VT) {
return false; return false;
VT = evt.getSimpleVT(); VT = evt.getSimpleVT();
// Handle all legal types, i.e. a register that will directly hold this // This is a legal type, but it's not something we handle in fast-isel.
if (VT == MVT::f128)
return false;
// Handle all other legal types, i.e. a register that will directly hold this
// value. // value.
return TLI.isTypeLegal(VT); return TLI.isTypeLegal(VT);
} }
@@ -1107,6 +1114,8 @@ bool ARM64FastISel::SelectFPToInt(const Instruction *I, bool Signed) {
return false; return false;
EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType(), true); EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType(), true);
if (SrcVT == MVT::f128)
return false;
unsigned Opc; unsigned Opc;
if (SrcVT == MVT::f64) { if (SrcVT == MVT::f64) {
@@ -1132,6 +1141,8 @@ bool ARM64FastISel::SelectIntToFP(const Instruction *I, bool Signed) {
MVT DestVT; MVT DestVT;
if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector()) if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())
return false; return false;
assert ((DestVT == MVT::f32 || DestVT == MVT::f64) &&
"Unexpected value type.");
unsigned SrcReg = getRegForValue(I->getOperand(0)); unsigned SrcReg = getRegForValue(I->getOperand(0));
if (SrcReg == 0) if (SrcReg == 0)
@@ -1578,6 +1589,8 @@ bool ARM64FastISel::SelectRet(const Instruction *I) {
if (!RVEVT.isSimple()) if (!RVEVT.isSimple())
return false; return false;
MVT RVVT = RVEVT.getSimpleVT(); MVT RVVT = RVEVT.getSimpleVT();
if (RVVT == MVT::f128)
return false;
MVT DestVT = VA.getValVT(); MVT DestVT = VA.getValVT();
// Special handling for extended integers. // Special handling for extended integers.
if (RVVT != DestVT) { if (RVVT != DestVT) {

34
test/CodeGen/ARM64/fast-isel-noconvert.ll
View File

@@ -33,4 +33,36 @@ define <2 x i64> @test_fptosi(<2 x double> %in) {
%res = fptosi <2 x double> %in to <2 x i64> %res = fptosi <2 x double> %in to <2 x i64>
ret <2 x i64> %res ret <2 x i64> %res
} }
define fp128 @uitofp_i32_fp128(i32 %a) {
entry:
; CHECK-LABEL: uitofp_i32_fp128
; CHECK: bl ___floatunsitf
%conv = uitofp i32 %a to fp128
ret fp128 %conv
}
define fp128 @uitofp_i64_fp128(i64 %a) {
entry:
; CHECK-LABEL: uitofp_i64_fp128
; CHECK: bl ___floatunditf
%conv = uitofp i64 %a to fp128
ret fp128 %conv
}
define i32 @uitofp_fp128_i32(fp128 %a) {
entry:
; CHECK-LABEL: uitofp_fp128_i32
; CHECK: ___fixunstfsi
%conv = fptoui fp128 %a to i32
ret i32 %conv
}
define i64 @uitofp_fp128_i64(fp128 %a) {
entry:
; CHECK-LABEL: uitofp_fp128_i64
; CHECK: ___fixunstfdi
%conv = fptoui fp128 %a to i64
ret i64 %conv
}