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[mips][sched] Renamed II_FsqrtSingle and II_FsqrtDouble to II_SQRT_S and II_SQRT_D respectively

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No functional change



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199741 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders 2014-01-21 13:36:45 +00:00
parent fa458d8ad2
commit faacfecf60
3 changed files with 10 additions and 10 deletions
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6
lib/Target/Mips/MicroMipsInstrFPU.td
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@ -52,7 +52,7 @@ def ROUND_W_S_MM : MMRel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>,
ROUND_W_FM_MM<0, 0xec>; ROUND_W_FM_MM<0, 0xec>;
def TRUNC_W_S_MM : MMRel, ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, II_TRUNC>, def TRUNC_W_S_MM : MMRel, ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, II_TRUNC>,
ROUND_W_FM_MM<0, 0xac>; ROUND_W_FM_MM<0, 0xac>;
def FSQRT_S_MM : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd,IIFsqrtSingle, def FSQRT_S_MM : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S,
fsqrt>, ROUND_W_FM_MM<0, 0x28>; fsqrt>, ROUND_W_FM_MM<0, 0x28>;
def CEIL_W_MM : MMRel, ABSS_FT<"ceil.w.d", FGR32Opnd, AFGR64Opnd, II_CEIL>, def CEIL_W_MM : MMRel, ABSS_FT<"ceil.w.d", FGR32Opnd, AFGR64Opnd, II_CEIL>,
@ -66,8 +66,8 @@ def ROUND_W_MM : MMRel, ABSS_FT<"round.w.d", FGR32Opnd, AFGR64Opnd, II_ROUND>,
def TRUNC_W_MM : MMRel, ABSS_FT<"trunc.w.d", FGR32Opnd, AFGR64Opnd, II_TRUNC>, def TRUNC_W_MM : MMRel, ABSS_FT<"trunc.w.d", FGR32Opnd, AFGR64Opnd, II_TRUNC>,
ROUND_W_FM_MM<1, 0xac>; ROUND_W_FM_MM<1, 0xac>;
def FSQRT_MM : MMRel, ABSS_FT<"sqrt.d", AFGR64Opnd, AFGR64Opnd, def FSQRT_MM : MMRel, ABSS_FT<"sqrt.d", AFGR64Opnd, AFGR64Opnd, II_SQRT_D,
IIFsqrtDouble, fsqrt>, ROUND_W_FM_MM<1, 0x28>; fsqrt>, ROUND_W_FM_MM<1, 0x28>;
def CVT_L_S_MM : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>, def CVT_L_S_MM : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>,
ROUND_W_FM_MM<0, 0x4>; ROUND_W_FM_MM<0, 0x4>;

6
lib/Target/Mips/MipsInstrFPU.td
View File

@ -331,9 +331,9 @@ let Predicates = [NoNaNsFPMath, HasStdEnc] in {
defm FNEG : ABSS_M<"neg.d", II_NEG, fneg>, ABSS_FM<0x7, 17>; defm FNEG : ABSS_M<"neg.d", II_NEG, fneg>, ABSS_FM<0x7, 17>;
} }
def FSQRT_S : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, IIFsqrtSingle, def FSQRT_S : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S, fsqrt>,
fsqrt>, ABSS_FM<0x4, 16>; ABSS_FM<0x4, 16>;
defm FSQRT : ABSS_M<"sqrt.d", IIFsqrtDouble, fsqrt>, ABSS_FM<0x4, 17>; defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, fsqrt>, ABSS_FM<0x4, 17>;
// The odd-numbered registers are only referenced when doing loads, // The odd-numbered registers are only referenced when doing loads,
// stores, and moves between floating-point and integer registers. // stores, and moves between floating-point and integer registers.

8
lib/Target/Mips/MipsSchedule.td
View File

@ -20,8 +20,6 @@ def IIAlu : InstrItinClass;
def IILoad : InstrItinClass; def IILoad : InstrItinClass;
def IIStore : InstrItinClass; def IIStore : InstrItinClass;
def IIBranch : InstrItinClass; def IIBranch : InstrItinClass;
def IIFsqrtSingle : InstrItinClass;
def IIFsqrtDouble : InstrItinClass;
def IIFrecipFsqrtStep : InstrItinClass; def IIFrecipFsqrtStep : InstrItinClass;
def IIFLoad : InstrItinClass; def IIFLoad : InstrItinClass;
def IIFStore : InstrItinClass; def IIFStore : InstrItinClass;
@ -116,6 +114,8 @@ def II_SLL : InstrItinClass;
def II_SLLV : InstrItinClass; def II_SLLV : InstrItinClass;
def II_SLTI_SLTIU : InstrItinClass; // slti and sltiu def II_SLTI_SLTIU : InstrItinClass; // slti and sltiu
def II_SLT_SLTU : InstrItinClass; // slt and sltu def II_SLT_SLTU : InstrItinClass; // slt and sltu
def II_SQRT_D : InstrItinClass;
def II_SQRT_S : InstrItinClass;
def II_SRA : InstrItinClass; def II_SRA : InstrItinClass;
def II_SRAV : InstrItinClass; def II_SRAV : InstrItinClass;
def II_SRL : InstrItinClass; def II_SRL : InstrItinClass;
@ -227,8 +227,8 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
InstrItinData<II_NMSUB_D , [InstrStage<8, [ALU]>]>, InstrItinData<II_NMSUB_D , [InstrStage<8, [ALU]>]>,
InstrItinData<II_DIV_S , [InstrStage<23, [ALU]>]>, InstrItinData<II_DIV_S , [InstrStage<23, [ALU]>]>,
InstrItinData<II_DIV_D , [InstrStage<36, [ALU]>]>, InstrItinData<II_DIV_D , [InstrStage<36, [ALU]>]>,
InstrItinData<IIFsqrtSingle , [InstrStage<54, [ALU]>]>, InstrItinData<II_SQRT_S , [InstrStage<54, [ALU]>]>,
InstrItinData<IIFsqrtDouble , [InstrStage<12, [ALU]>]>, InstrItinData<II_SQRT_D , [InstrStage<12, [ALU]>]>,
InstrItinData<IIFrecipFsqrtStep , [InstrStage<5, [ALU]>]>, InstrItinData<IIFrecipFsqrtStep , [InstrStage<5, [ALU]>]>,
InstrItinData<IIFLoad , [InstrStage<3, [ALU]>]>, InstrItinData<IIFLoad , [InstrStage<3, [ALU]>]>,
InstrItinData<IIFStore , [InstrStage<1, [ALU]>]>, InstrItinData<IIFStore , [InstrStage<1, [ALU]>]>,