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https://github.com/c64scene-ar/llvm-6502.git
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Add patterns for selecting TBM instructions from logical operations. Patch from Yunzhong Gao.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191871 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
da750239bd
commit
fafe4bbd6c
@ -2602,7 +2602,7 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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llvm_i32_ty], [IntrNoMem]>;
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def int_x86_tbm_bextri_u64 : GCCBuiltin<"__builtin_ia32_bextri_u64">,
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Intrinsic<[llvm_i64_ty], [llvm_i64_ty,
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llvm_i32_ty], [IntrNoMem]>;
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llvm_i64_ty], [IntrNoMem]>;
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def int_x86_tbm_blcfill_u32 : GCCBuiltin<"__builtin_ia32_blcfill_u32">,
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Intrinsic<[llvm_i32_ty], [llvm_i32_ty],
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[IntrNoMem]>;
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@ -17578,22 +17578,6 @@ static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
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if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
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isAllOnes(N1.getOperand(1)))
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return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
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// Check for BEXTR
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if (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL) {
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ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
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ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
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if (MaskNode && ShiftNode) {
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uint64_t Mask = MaskNode->getZExtValue();
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uint64_t Shift = ShiftNode->getZExtValue();
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if (isMask_64(Mask)) {
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uint64_t MaskSize = CountPopulation_64(Mask);
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if (Shift + MaskSize <= VT.getSizeInBits())
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return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
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DAG.getConstant(Shift | (MaskSize << 8), VT));
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}
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}
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}
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}
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if (Subtarget->hasBMI2()) {
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@ -17622,6 +17606,23 @@ static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
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}
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}
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// Check for BEXTR.
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if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
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(N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
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ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
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ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
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if (MaskNode && ShiftNode) {
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uint64_t Mask = MaskNode->getZExtValue();
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uint64_t Shift = ShiftNode->getZExtValue();
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if (isMask_64(Mask)) {
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uint64_t MaskSize = CountPopulation_64(Mask);
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if (Shift + MaskSize <= VT.getSizeInBits())
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return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
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DAG.getConstant(Shift | (MaskSize << 8), VT));
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}
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}
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} // BEXTR
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return SDValue();
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}
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@ -1875,14 +1875,16 @@ def : Pat<(X86bzhi (loadi64 addr:$src1), GR8:$src2),
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(BZHI64rm addr:$src1,
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
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def : Pat<(X86bextr GR32:$src1, GR32:$src2),
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(BEXTR32rr GR32:$src1, GR32:$src2)>;
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def : Pat<(X86bextr (loadi32 addr:$src1), GR32:$src2),
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(BEXTR32rm addr:$src1, GR32:$src2)>;
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def : Pat<(X86bextr GR64:$src1, GR64:$src2),
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(BEXTR64rr GR64:$src1, GR64:$src2)>;
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def : Pat<(X86bextr (loadi64 addr:$src1), GR64:$src2),
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(BEXTR64rm addr:$src1, GR64:$src2)>;
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let Predicates = [HasBMI] in {
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def : Pat<(X86bextr GR32:$src1, GR32:$src2),
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(BEXTR32rr GR32:$src1, GR32:$src2)>;
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def : Pat<(X86bextr (loadi32 addr:$src1), GR32:$src2),
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(BEXTR32rm addr:$src1, GR32:$src2)>;
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def : Pat<(X86bextr GR64:$src1, GR64:$src2),
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(BEXTR64rr GR64:$src1, GR64:$src2)>;
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def : Pat<(X86bextr (loadi64 addr:$src1), GR64:$src2),
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(BEXTR64rm addr:$src1, GR64:$src2)>;
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} // HasBMI
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multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC,
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X86MemOperand x86memop, Intrinsic Int,
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@ -1914,24 +1916,26 @@ let isAsmParserOnly = 1, Predicates = [HasTBM], Defs = [EFLAGS] in {
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multiclass tbm_ternary_imm_intr<bits<8> opc, RegisterClass RC, string OpcodeStr,
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X86MemOperand x86memop, PatFrag ld_frag,
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Intrinsic Int> {
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def rr : Ii32<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, i32imm:$cntl),
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Intrinsic Int, Operand immtype,
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SDPatternOperator immoperator> {
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def ri : Ii32<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, immtype:$cntl),
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!strconcat(OpcodeStr,
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"\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
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[(set RC:$dst, (Int RC:$src1, imm:$cntl))]>,
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[(set RC:$dst, (Int RC:$src1, immoperator:$cntl))]>,
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XOP, XOPA, VEX;
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def mr : Ii32<opc, MRMSrcMem, (outs RC:$dst),
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(ins x86memop:$src1, i32imm:$cntl),
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def mi : Ii32<opc, MRMSrcMem, (outs RC:$dst),
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(ins x86memop:$src1, immtype:$cntl),
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!strconcat(OpcodeStr,
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"\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
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[(set RC:$dst, (Int (ld_frag addr:$src1), imm:$cntl))]>,
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[(set RC:$dst, (Int (ld_frag addr:$src1), immoperator:$cntl))]>,
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XOP, XOPA, VEX;
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}
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defm BEXTRI32 : tbm_ternary_imm_intr<0x10, GR32, "bextr", i32mem, loadi32,
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int_x86_tbm_bextri_u32>;
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int_x86_tbm_bextri_u32, i32imm, imm>;
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defm BEXTRI64 : tbm_ternary_imm_intr<0x10, GR64, "bextr", i64mem, loadi64,
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int_x86_tbm_bextri_u64>, VEX_W;
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int_x86_tbm_bextri_u64, i64i32imm,
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i64immSExt32>, VEX_W;
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multiclass tbm_binary_rm<bits<8> opc, Format FormReg, Format FormMem,
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RegisterClass RC, string OpcodeStr,
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@ -1985,6 +1989,67 @@ defm TZMSK : tbm_binary_intr<0x01, "tzmsk", MRM4r, MRM4m,
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int_x86_tbm_tzmsk_u64>;
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} // isAsmParserOnly, HasTBM, EFLAGS
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//===----------------------------------------------------------------------===//
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// Pattern fragments to auto generate TBM instructions.
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//===----------------------------------------------------------------------===//
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let Predicates = [HasTBM] in {
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def : Pat<(X86bextr GR32:$src1, (i32 imm:$src2)),
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(BEXTRI32ri GR32:$src1, imm:$src2)>;
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def : Pat<(X86bextr (loadi32 addr:$src1), (i32 imm:$src2)),
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(BEXTRI32mi addr:$src1, imm:$src2)>;
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def : Pat<(X86bextr GR64:$src1, i64immSExt32:$src2),
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(BEXTRI64ri GR64:$src1, i64immSExt32:$src2)>;
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def : Pat<(X86bextr (loadi64 addr:$src1), i64immSExt32:$src2),
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(BEXTRI64mi addr:$src1, i64immSExt32:$src2)>;
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// FIXME: patterns for the load versions are not implemented
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def : Pat<(and GR32:$src, (add GR32:$src, 1)),
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(BLCFILL_32rr GR32:$src)>;
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def : Pat<(and GR64:$src, (add GR64:$src, 1)),
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(BLCFILL_64rr GR64:$src)>;
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def : Pat<(or GR32:$src, (not (add GR32:$src, 1))),
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(BLCI_32rr GR32:$src)>;
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def : Pat<(or GR64:$src, (not (add GR64:$src, 1))),
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(BLCI_64rr GR64:$src)>;
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def : Pat<(and (not GR32:$src), (add GR32:$src, 1)),
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(BLCIC_32rr GR32:$src)>;
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def : Pat<(and (not GR64:$src), (add GR64:$src, 1)),
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(BLCIC_64rr GR64:$src)>;
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def : Pat<(xor GR32:$src, (add GR32:$src, 1)),
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(BLCMSK_32rr GR32:$src)>;
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def : Pat<(xor GR64:$src, (add GR64:$src, 1)),
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(BLCMSK_64rr GR64:$src)>;
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def : Pat<(or GR32:$src, (add GR32:$src, 1)),
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(BLCS_32rr GR32:$src)>;
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def : Pat<(or GR64:$src, (add GR64:$src, 1)),
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(BLCS_64rr GR64:$src)>;
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def : Pat<(or GR32:$src, (add GR32:$src, -1)),
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(BLSFILL_32rr GR32:$src)>;
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def : Pat<(or GR64:$src, (add GR64:$src, -1)),
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(BLSFILL_64rr GR64:$src)>;
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def : Pat<(or (not GR32:$src), (add GR32:$src, -1)),
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(BLSIC_32rr GR32:$src)>;
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def : Pat<(or (not GR64:$src), (add GR64:$src, -1)),
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(BLSIC_64rr GR64:$src)>;
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def : Pat<(or (not GR32:$src), (add GR32:$src, 1)),
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(T1MSKC_32rr GR32:$src)>;
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def : Pat<(or (not GR64:$src), (add GR64:$src, 1)),
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(T1MSKC_64rr GR64:$src)>;
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def : Pat<(and (not GR32:$src), (add GR32:$src, -1)),
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(TZMSK_32rr GR32:$src)>;
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def : Pat<(and (not GR64:$src), (add GR64:$src, -1)),
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(TZMSK_64rr GR64:$src)>;
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} // HasTBM
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//===----------------------------------------------------------------------===//
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// Subsystems.
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//===----------------------------------------------------------------------===//
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@ -26,11 +26,11 @@ entry:
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; CHECK-LABEL: test_x86_tbm_bextri_u64:
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; CHECK-NOT: mov
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; CHECK: bextr $
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%0 = tail call i64 @llvm.x86.tbm.bextri.u64(i64 %a, i32 2814)
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%0 = tail call i64 @llvm.x86.tbm.bextri.u64(i64 %a, i64 2814)
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ret i64 %0
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}
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declare i64 @llvm.x86.tbm.bextri.u64(i64, i32) nounwind readnone
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declare i64 @llvm.x86.tbm.bextri.u64(i64, i64) nounwind readnone
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define i64 @test_x86_tbm_bextri_u64_m(i64* nocapture %a) nounwind readonly {
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entry:
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@ -38,7 +38,7 @@ entry:
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; CHECK-NOT: mov
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; CHECK: bextr $
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%tmp1 = load i64* %a, align 8
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%0 = tail call i64 @llvm.x86.tbm.bextri.u64(i64 %tmp1, i32 2814)
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%0 = tail call i64 @llvm.x86.tbm.bextri.u64(i64 %tmp1, i64 2814)
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ret i64 %0
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}
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466
test/CodeGen/X86/tbm_patterns.ll
Normal file
466
test/CodeGen/X86/tbm_patterns.ll
Normal file
@ -0,0 +1,466 @@
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; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+tbm < %s | FileCheck %s
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define i32 @test_x86_tbm_bextri_u32(i32 %a) nounwind readnone {
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entry:
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; CHECK-LABEL: test_x86_tbm_bextri_u32:
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; CHECK-NOT: mov
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; CHECK: bextr $
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%0 = lshr i32 %a, 4
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%1 = and i32 %0, 4095
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ret i32 %1
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}
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define i32 @test_x86_tbm_bextri_u32_m(i32* nocapture %a) nounwind readonly {
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entry:
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; CHECK-LABEL: test_x86_tbm_bextri_u32_m:
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; CHECK-NOT: mov
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; CHECK: bextr $
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%0 = load i32* %a
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%1 = lshr i32 %0, 4
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%2 = and i32 %1, 4095
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ret i32 %2
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}
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define i64 @test_x86_tbm_bextri_u64(i64 %a) nounwind readnone {
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entry:
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; CHECK-LABEL: test_x86_tbm_bextri_u64:
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; CHECK-NOT: mov
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; CHECK: bextr $
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%0 = lshr i64 %a, 4
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%1 = and i64 %0, 4095
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ret i64 %1
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}
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define i64 @test_x86_tbm_bextri_u64_m(i64* nocapture %a) nounwind readonly {
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entry:
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; CHECK-LABEL: test_x86_tbm_bextri_u64_m:
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; CHECK-NOT: mov
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; CHECK: bextr $
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%0 = load i64* %a
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%1 = lshr i64 %0, 4
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%2 = and i64 %1, 4095
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ret i64 %2
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}
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define i32 @test_x86_tbm_blcfill_u32(i32 %a) nounwind readnone {
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entry:
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; CHECK-LABEL: test_x86_tbm_blcfill_u32:
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; CHECK-NOT: mov
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; CHECK: blcfill %
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%0 = add i32 %a, 1
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%1 = and i32 %0, %a
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ret i32 %1
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}
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define i64 @test_x86_tbm_blcfill_u64(i64 %a) nounwind readnone {
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entry:
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; CHECK-LABEL: test_x86_tbm_blcfill_u64:
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; CHECK-NOT: mov
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; CHECK: blcfill %
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%0 = add i64 %a, 1
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%1 = and i64 %0, %a
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ret i64 %1
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}
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define i32 @test_x86_tbm_blci_u32(i32 %a) nounwind readnone {
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entry:
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; CHECK-LABEL: test_x86_tbm_blci_u32:
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; CHECK-NOT: mov
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; CHECK: blci %
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%0 = add i32 1, %a
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%1 = xor i32 %0, -1
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%2 = or i32 %1, %a
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ret i32 %2
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}
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define i64 @test_x86_tbm_blci_u64(i64 %a) nounwind readnone {
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entry:
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; CHECK-LABEL: test_x86_tbm_blci_u64:
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; CHECK-NOT: mov
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; CHECK: blci %
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%0 = add i64 1, %a
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%1 = xor i64 %0, -1
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%2 = or i64 %1, %a
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ret i64 %2
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}
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define i32 @test_x86_tbm_blcic_u32(i32 %a) nounwind readnone {
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entry:
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; CHECK-LABEL: test_x86_tbm_blcic_u32:
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; CHECK-NOT: mov
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; CHECK: blcic %
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%0 = xor i32 %a, -1
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%1 = add i32 %a, 1
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%2 = and i32 %1, %0
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ret i32 %2
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}
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define i64 @test_x86_tbm_blcic_u64(i64 %a) nounwind readnone {
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entry:
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; CHECK-LABEL: test_x86_tbm_blcic_u64:
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; CHECK-NOT: mov
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; CHECK: blcic %
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%0 = xor i64 %a, -1
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%1 = add i64 %a, 1
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%2 = and i64 %1, %0
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ret i64 %2
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}
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define i32 @test_x86_tbm_blcmsk_u32(i32 %a) nounwind readnone {
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entry:
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; CHECK-LABEL: test_x86_tbm_blcmsk_u32:
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; CHECK-NOT: mov
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; CHECK: blcmsk %
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%0 = add i32 %a, 1
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%1 = xor i32 %0, %a
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ret i32 %1
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}
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define i64 @test_x86_tbm_blcmsk_u64(i64 %a) nounwind readnone {
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entry:
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; CHECK-LABEL: test_x86_tbm_blcmsk_u64:
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; CHECK-NOT: mov
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; CHECK: blcmsk %
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%0 = add i64 %a, 1
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%1 = xor i64 %0, %a
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ret i64 %1
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}
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define i32 @test_x86_tbm_blcs_u32(i32 %a) nounwind readnone {
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entry:
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; CHECK-LABEL: test_x86_tbm_blcs_u32:
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; CHECK-NOT: mov
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; CHECK: blcs %
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%0 = add i32 %a, 1
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%1 = or i32 %0, %a
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ret i32 %1
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}
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define i64 @test_x86_tbm_blcs_u64(i64 %a) nounwind readnone {
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entry:
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; CHECK-LABEL: test_x86_tbm_blcs_u64:
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; CHECK-NOT: mov
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; CHECK: blcs %
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%0 = add i64 %a, 1
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%1 = or i64 %0, %a
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ret i64 %1
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}
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define i32 @test_x86_tbm_blsfill_u32(i32 %a) nounwind readnone {
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entry:
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; CHECK-LABEL: test_x86_tbm_blsfill_u32:
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; CHECK-NOT: mov
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; CHECK: blsfill %
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%0 = add i32 %a, -1
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%1 = or i32 %0, %a
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ret i32 %1
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}
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define i64 @test_x86_tbm_blsfill_u64(i64 %a) nounwind readnone {
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entry:
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; CHECK-LABEL: test_x86_tbm_blsfill_u64:
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; CHECK-NOT: mov
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; CHECK: blsfill %
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%0 = add i64 %a, -1
|
||||
%1 = or i64 %0, %a
|
||||
ret i64 %1
|
||||
}
|
||||
|
||||
define i32 @test_x86_tbm_blsic_u32(i32 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-LABEL: test_x86_tbm_blsic_u32:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: blsic %
|
||||
%0 = xor i32 %a, -1
|
||||
%1 = add i32 %a, -1
|
||||
%2 = or i32 %0, %1
|
||||
ret i32 %2
|
||||
}
|
||||
|
||||
define i64 @test_x86_tbm_blsic_u64(i64 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-LABEL: test_x86_tbm_blsic_u64:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: blsic %
|
||||
%0 = xor i64 %a, -1
|
||||
%1 = add i64 %a, -1
|
||||
%2 = or i64 %0, %1
|
||||
ret i64 %2
|
||||
}
|
||||
|
||||
define i32 @test_x86_tbm_t1mskc_u32(i32 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-LABEL: test_x86_tbm_t1mskc_u32:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: t1mskc %
|
||||
%0 = xor i32 %a, -1
|
||||
%1 = add i32 %a, 1
|
||||
%2 = or i32 %0, %1
|
||||
ret i32 %2
|
||||
}
|
||||
|
||||
define i64 @Ttest_x86_tbm_t1mskc_u64(i64 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-LABEL: test_x86_tbm_t1mskc_u64:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: t1mskc %
|
||||
%0 = xor i64 %a, -1
|
||||
%1 = add i64 %a, 1
|
||||
%2 = or i64 %0, %1
|
||||
ret i64 %2
|
||||
}
|
||||
|
||||
define i32 @test_x86_tbm_tzmsk_u32(i32 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-LABEL: test_x86_tbm_tzmsk_u32:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: tzmsk %
|
||||
%0 = xor i32 %a, -1
|
||||
%1 = add i32 %a, -1
|
||||
%2 = and i32 %0, %1
|
||||
ret i32 %2
|
||||
}
|
||||
|
||||
define i64 @test_x86_tbm_tzmsk_u64(i64 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-LABEL: test_x86_tbm_tzmsk_u64:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: tzmsk %
|
||||
%0 = xor i64 %a, -1
|
||||
%1 = add i64 %a, -1
|
||||
%2 = and i64 %0, %1
|
||||
ret i64 %2
|
||||
}
|
||||
; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+tbm < %s | FileCheck %s
|
||||
|
||||
define i32 @test_x86_tbm_bextri_u32(i32 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-LABEL: test_x86_tbm_bextri_u32:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: bextr $
|
||||
%0 = lshr i32 %a, 4
|
||||
%1 = and i32 %0, 4095
|
||||
ret i32 %1
|
||||
}
|
||||
|
||||
define i32 @test_x86_tbm_bextri_u32_m(i32* nocapture %a) nounwind readonly {
|
||||
entry:
|
||||
; CHECK-LABEL: test_x86_tbm_bextri_u32_m:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: bextr $
|
||||
%0 = load i32* %a
|
||||
%1 = lshr i32 %0, 4
|
||||
%2 = and i32 %1, 4095
|
||||
ret i32 %2
|
||||
}
|
||||
|
||||
define i64 @test_x86_tbm_bextri_u64(i64 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-LABEL: test_x86_tbm_bextri_u64:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: bextr $
|
||||
%0 = lshr i64 %a, 4
|
||||
%1 = and i64 %0, 4095
|
||||
ret i64 %1
|
||||
}
|
||||
|
||||
define i64 @test_x86_tbm_bextri_u64_m(i64* nocapture %a) nounwind readonly {
|
||||
entry:
|
||||
; CHECK-LABEL: test_x86_tbm_bextri_u64_m:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: bextr $
|
||||
%0 = load i64* %a
|
||||
%1 = lshr i64 %0, 4
|
||||
%2 = and i64 %1, 4095
|
||||
ret i64 %2
|
||||
}
|
||||
|
||||
define i32 @test_x86_tbm_blcfill_u32(i32 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-LABEL: test_x86_tbm_blcfill_u32:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: blcfill %
|
||||
%0 = add i32 %a, 1
|
||||
%1 = and i32 %0, %a
|
||||
ret i32 %1
|
||||
}
|
||||
|
||||
define i64 @test_x86_tbm_blcfill_u64(i64 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-LABEL: test_x86_tbm_blcfill_u64:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: blcfill %
|
||||
%0 = add i64 %a, 1
|
||||
%1 = and i64 %0, %a
|
||||
ret i64 %1
|
||||
}
|
||||
|
||||
define i32 @test_x86_tbm_blci_u32(i32 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-LABEL: test_x86_tbm_blci_u32:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: blci %
|
||||
%0 = add i32 1, %a
|
||||
%1 = xor i32 %0, -1
|
||||
%2 = or i32 %1, %a
|
||||
ret i32 %2
|
||||
}
|
||||
|
||||
define i64 @test_x86_tbm_blci_u64(i64 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-LABEL: test_x86_tbm_blci_u64:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: blci %
|
||||
%0 = add i64 1, %a
|
||||
%1 = xor i64 %0, -1
|
||||
%2 = or i64 %1, %a
|
||||
ret i64 %2
|
||||
}
|
||||
|
||||
define i32 @test_x86_tbm_blcic_u32(i32 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-LABEL: test_x86_tbm_blcic_u32:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: blcic %
|
||||
%0 = xor i32 %a, -1
|
||||
%1 = add i32 %a, 1
|
||||
%2 = and i32 %1, %0
|
||||
ret i32 %2
|
||||
}
|
||||
|
||||
define i64 @test_x86_tbm_blcic_u64(i64 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-LABEL: test_x86_tbm_blcic_u64:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: blcic %
|
||||
%0 = xor i64 %a, -1
|
||||
%1 = add i64 %a, 1
|
||||
%2 = and i64 %1, %0
|
||||
ret i64 %2
|
||||
}
|
||||
|
||||
define i32 @test_x86_tbm_blcmsk_u32(i32 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-LABEL: test_x86_tbm_blcmsk_u32:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: blcmsk %
|
||||
%0 = add i32 %a, 1
|
||||
%1 = xor i32 %0, %a
|
||||
ret i32 %1
|
||||
}
|
||||
|
||||
define i64 @test_x86_tbm_blcmsk_u64(i64 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-LABEL: test_x86_tbm_blcmsk_u64:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: blcmsk %
|
||||
%0 = add i64 %a, 1
|
||||
%1 = xor i64 %0, %a
|
||||
ret i64 %1
|
||||
}
|
||||
|
||||
define i32 @test_x86_tbm_blcs_u32(i32 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-LABEL: test_x86_tbm_blcs_u32:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: blcs %
|
||||
%0 = add i32 %a, 1
|
||||
%1 = or i32 %0, %a
|
||||
ret i32 %1
|
||||
}
|
||||
|
||||
define i64 @test_x86_tbm_blcs_u64(i64 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-LABEL: test_x86_tbm_blcs_u64:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: blcs %
|
||||
%0 = add i64 %a, 1
|
||||
%1 = or i64 %0, %a
|
||||
ret i64 %1
|
||||
}
|
||||
|
||||
define i32 @test_x86_tbm_blsfill_u32(i32 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-LABEL: test_x86_tbm_blsfill_u32:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: blsfill %
|
||||
%0 = add i32 %a, -1
|
||||
%1 = or i32 %0, %a
|
||||
ret i32 %1
|
||||
}
|
||||
|
||||
define i64 @test_x86_tbm_blsfill_u64(i64 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-LABEL: test_x86_tbm_blsfill_u64:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: blsfill %
|
||||
%0 = add i64 %a, -1
|
||||
%1 = or i64 %0, %a
|
||||
ret i64 %1
|
||||
}
|
||||
|
||||
define i32 @test_x86_tbm_blsic_u32(i32 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-LABEL: test_x86_tbm_blsic_u32:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: blsic %
|
||||
%0 = xor i32 %a, -1
|
||||
%1 = add i32 %a, -1
|
||||
%2 = or i32 %0, %1
|
||||
ret i32 %2
|
||||
}
|
||||
|
||||
define i64 @test_x86_tbm_blsic_u64(i64 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-LABEL: test_x86_tbm_blsic_u64:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: blsic %
|
||||
%0 = xor i64 %a, -1
|
||||
%1 = add i64 %a, -1
|
||||
%2 = or i64 %0, %1
|
||||
ret i64 %2
|
||||
}
|
||||
|
||||
define i32 @test_x86_tbm_t1mskc_u32(i32 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-LABEL: test_x86_tbm_t1mskc_u32:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: t1mskc %
|
||||
%0 = xor i32 %a, -1
|
||||
%1 = add i32 %a, 1
|
||||
%2 = or i32 %0, %1
|
||||
ret i32 %2
|
||||
}
|
||||
|
||||
define i64 @Ttest_x86_tbm_t1mskc_u64(i64 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-LABEL: test_x86_tbm_t1mskc_u64:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: t1mskc %
|
||||
%0 = xor i64 %a, -1
|
||||
%1 = add i64 %a, 1
|
||||
%2 = or i64 %0, %1
|
||||
ret i64 %2
|
||||
}
|
||||
|
||||
define i32 @test_x86_tbm_tzmsk_u32(i32 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-LABEL: test_x86_tbm_tzmsk_u32:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: tzmsk %
|
||||
%0 = xor i32 %a, -1
|
||||
%1 = add i32 %a, -1
|
||||
%2 = and i32 %0, %1
|
||||
ret i32 %2
|
||||
}
|
||||
|
||||
define i64 @test_x86_tbm_tzmsk_u64(i64 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-LABEL: test_x86_tbm_tzmsk_u64:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: tzmsk %
|
||||
%0 = xor i64 %a, -1
|
||||
%1 = add i64 %a, -1
|
||||
%2 = and i64 %0, %1
|
||||
ret i64 %2
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user