6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-10 18:34:09 +00:00
Code Issues Projects Releases Wiki Activity

Remove unneeded stuff from GRAD register class.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59311 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dale Johannesen 2008-11-14 18:10:48 +00:00
parent 30aa75c96a
commit fb88f1f9a7
1 changed files with 1 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
lib/Target/X86/X86RegisterInfo.td
View File

@ -441,25 +441,7 @@ def GR32_ : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]> {
}
// A class to support the 'A' assembler constraint: EAX then EDX.
def GRAD : RegisterClass<"X86", [i32], 32, [EAX, EDX]> {
let MethodProtos = [{
iterator allocation_order_begin(const MachineFunction &MF) const;
iterator allocation_order_end(const MachineFunction &MF) const;
}];
let MethodBodies = [{
static const unsigned X86_GRAD_AO[] = {X86::EAX, X86::EDX};
GRADClass::iterator
GRADClass::allocation_order_begin(const MachineFunction &MF) const {
return X86_GRAD_AO;
}
GRADClass::iterator
GRADClass::allocation_order_end(const MachineFunction &MF) const {
return X86_GRAD_AO + (sizeof(X86_GRAD_AO) / sizeof(unsigned));
}
}];
}
def GRAD : RegisterClass<"X86", [i32], 32, [EAX, EDX]>;
// Scalar SSE2 floating point registers.
def FR32 : RegisterClass<"X86", [f32], 32,