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Changes for MachineBasicBlock to use SortedVector for LiveIns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243389 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -14,6 +14,7 @@
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#ifndef LLVM_CODEGEN_MACHINEBASICBLOCK_H
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#ifndef LLVM_CODEGEN_MACHINEBASICBLOCK_H
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#define LLVM_CODEGEN_MACHINEBASICBLOCK_H
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#define LLVM_CODEGEN_MACHINEBASICBLOCK_H
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#include "llvm/ADT/SortedVector.h"
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#include "llvm/ADT/GraphTraits.h"
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#include "llvm/ADT/GraphTraits.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/Support/DataTypes.h"
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#include "llvm/Support/DataTypes.h"
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@ -80,7 +81,7 @@ class MachineBasicBlock : public ilist_node<MachineBasicBlock> {
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/// LiveIns - Keep track of the physical registers that are livein of
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/// LiveIns - Keep track of the physical registers that are livein of
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/// the basicblock.
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/// the basicblock.
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std::vector<unsigned> LiveIns;
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mutable SortedVector<unsigned> LiveIns;
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/// Alignment - Alignment of the basic block. Zero if the basic block does
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/// Alignment - Alignment of the basic block. Zero if the basic block does
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/// not need to be aligned.
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/// not need to be aligned.
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@ -318,15 +319,12 @@ public:
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/// Adds the specified register as a live in. Note that it is an error to add
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/// Adds the specified register as a live in. Note that it is an error to add
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/// the same register to the same set more than once unless the intention is
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/// the same register to the same set more than once unless the intention is
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/// to call sortUniqueLiveIns after all registers are added.
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/// to call sortUniqueLiveIns after all registers are added.
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void addLiveIn(unsigned Reg) { LiveIns.push_back(Reg); }
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void addLiveIn(unsigned Reg) { LiveIns.insert(Reg); }
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/// Sorts and uniques the LiveIns vector. It can be significantly faster to do
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/// Sorts and uniques the LiveIns vector. It can be significantly faster to do
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/// this than repeatedly calling isLiveIn before calling addLiveIn for every
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/// this than repeatedly calling isLiveIn before calling addLiveIn for every
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/// LiveIn insertion.
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/// LiveIn insertion.
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void sortUniqueLiveIns() {
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void sortUniqueLiveIns() { LiveIns.sortUnique(); }
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std::sort(LiveIns.begin(), LiveIns.end());
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LiveIns.erase(std::unique(LiveIns.begin(), LiveIns.end()), LiveIns.end());
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}
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/// Add PhysReg as live in to this block, and ensure that there is a copy of
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/// Add PhysReg as live in to this block, and ensure that there is a copy of
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/// PhysReg to a virtual register of class RC. Return the virtual register
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/// PhysReg to a virtual register of class RC. Return the virtual register
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@ -339,14 +337,20 @@ public:
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/// isLiveIn - Return true if the specified register is in the live in set.
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/// isLiveIn - Return true if the specified register is in the live in set.
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///
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///
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bool isLiveIn(unsigned Reg) const;
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bool isLiveIn(unsigned Reg) const { return LiveIns.has(Reg); }
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// Iteration support for live in sets. These sets are kept in sorted
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// Iteration support for live in sets. These sets are kept in sorted
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// order by their register number.
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// order by their register number.
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typedef std::vector<unsigned>::const_iterator livein_iterator;
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typedef std::vector<unsigned>::const_iterator livein_iterator;
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livein_iterator livein_begin() const { return LiveIns.begin(); }
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livein_iterator livein_end() const { return LiveIns.end(); }
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bool livein_empty() const { return LiveIns.empty(); }
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bool livein_empty() const { return LiveIns.empty(); }
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livein_iterator livein_begin() const {
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LiveIns.sortUnique();
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return LiveIns.begin();
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}
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livein_iterator livein_end() const {
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LiveIns.sortUnique();
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return LiveIns.end();
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}
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/// getAlignment - Return alignment of the basic block.
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/// getAlignment - Return alignment of the basic block.
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/// The alignment is specified as log2(bytes).
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/// The alignment is specified as log2(bytes).
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@ -332,11 +332,6 @@ void MachineBasicBlock::removeLiveIn(unsigned Reg) {
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LiveIns.erase(I);
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LiveIns.erase(I);
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}
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}
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bool MachineBasicBlock::isLiveIn(unsigned Reg) const {
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livein_iterator I = std::find(livein_begin(), livein_end(), Reg);
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return I != livein_end();
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}
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unsigned
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unsigned
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MachineBasicBlock::addLiveIn(unsigned PhysReg, const TargetRegisterClass *RC) {
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MachineBasicBlock::addLiveIn(unsigned PhysReg, const TargetRegisterClass *RC) {
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assert(getParent() && "MBB must be inserted in function");
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assert(getParent() && "MBB must be inserted in function");
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