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[arm fast-isel] Appease the machine verifier by using the proper register

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classes.  The associated test case still doesn't pass, but it does have far
fewer issues.
rdar://12719844

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168657 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier
2012-11-27 01:06:49 +00:00
parent bc43fe1efe
commit fc17ddd889
1 changed files with 10 additions and 4 deletions
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14
lib/Target/ARM/ARMFastISel.cpp
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@@ -563,7 +563,9 @@ unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) {
const ConstantInt *CI = cast<ConstantInt>(C); const ConstantInt *CI = cast<ConstantInt>(C);
if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getZExtValue())) { if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getZExtValue())) {
unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16; unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16;
unsigned ImmReg = createResultReg(TLI.getRegClassFor(MVT::i32)); const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass :
&ARM::GPRRegClass;
unsigned ImmReg = createResultReg(RC);
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(Opc), ImmReg) TII.get(Opc), ImmReg)
.addImm(CI->getZExtValue())); .addImm(CI->getZExtValue()));
@@ -2577,15 +2579,18 @@ unsigned ARMFastISel::ARMEmitIntExt(EVT SrcVT, unsigned SrcReg, EVT DestVT,
unsigned Opc; unsigned Opc;
bool isBoolZext = false; bool isBoolZext = false;
const TargetRegisterClass *RC = TLI.getRegClassFor(MVT::i32);
if (!SrcVT.isSimple()) return 0; if (!SrcVT.isSimple()) return 0;
switch (SrcVT.getSimpleVT().SimpleTy) { switch (SrcVT.getSimpleVT().SimpleTy) {
default: return 0; default: return 0;
case MVT::i16: case MVT::i16:
if (!Subtarget->hasV6Ops()) return 0; if (!Subtarget->hasV6Ops()) return 0;
if (isZExt) if (isZExt) {
Opc = isThumb2 ? ARM::t2UXTH : ARM::UXTH; Opc = isThumb2 ? ARM::t2UXTH : ARM::UXTH;
else } else {
Opc = isThumb2 ? ARM::t2SXTH : ARM::SXTH; Opc = isThumb2 ? ARM::t2SXTH : ARM::SXTH;
RC = isThumb2 ?&ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
}
break; break;
case MVT::i8: case MVT::i8:
if (!Subtarget->hasV6Ops()) return 0; if (!Subtarget->hasV6Ops()) return 0;
@@ -2597,13 +2602,14 @@ unsigned ARMFastISel::ARMEmitIntExt(EVT SrcVT, unsigned SrcReg, EVT DestVT,
case MVT::i1: case MVT::i1:
if (isZExt) { if (isZExt) {
Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri; Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass;
isBoolZext = true; isBoolZext = true;
break; break;
} }
return 0; return 0;
} }
unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::i32)); unsigned ResultReg = createResultReg(RC);
MachineInstrBuilder MIB; MachineInstrBuilder MIB;
MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg) MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg)
.addReg(SrcReg); .addReg(SrcReg);