diff --git a/lib/Target/Mips/MipsISelDAGToDAG.cpp b/lib/Target/Mips/MipsISelDAGToDAG.cpp index 2dc54fa9ad6..fcf29fd9b8d 100644 --- a/lib/Target/Mips/MipsISelDAGToDAG.cpp +++ b/lib/Target/Mips/MipsISelDAGToDAG.cpp @@ -93,6 +93,12 @@ bool MipsDAGToDAGISel::selectIntAddrMM(SDValue Addr, SDValue &Base, return false; } +bool MipsDAGToDAGISel::selectIntAddrMSA(SDValue Addr, SDValue &Base, + SDValue &Offset) const { + llvm_unreachable("Unimplemented function."); + return false; +} + bool MipsDAGToDAGISel::selectAddr16(SDNode *Parent, SDValue N, SDValue &Base, SDValue &Offset, SDValue &Alias) { llvm_unreachable("Unimplemented function."); diff --git a/lib/Target/Mips/MipsISelDAGToDAG.h b/lib/Target/Mips/MipsISelDAGToDAG.h index a4d9da532b2..4546182a24a 100644 --- a/lib/Target/Mips/MipsISelDAGToDAG.h +++ b/lib/Target/Mips/MipsISelDAGToDAG.h @@ -73,6 +73,10 @@ private: virtual bool selectIntAddrMM(SDValue Addr, SDValue &Base, SDValue &Offset) const; + /// Match addr+simm10 and addr + virtual bool selectIntAddrMSA(SDValue Addr, SDValue &Base, + SDValue &Offset) const; + virtual bool selectAddr16(SDNode *Parent, SDValue N, SDValue &Base, SDValue &Offset, SDValue &Alias); diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 04267cd063a..e4c6785aca9 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -247,6 +247,8 @@ def calltarget : Operand { let EncoderMethod = "getJumpTargetOpValue"; } +def simm10 : Operand; + def simm16 : Operand { let DecoderMethod= "DecodeSimm16"; } @@ -314,6 +316,7 @@ def mem : mem_generic; // MSA specific address operand def mem_msa : mem_generic { + let MIOperandInfo = (ops ptr_rc, simm10); let EncoderMethod = "getMSAMemEncoding"; } @@ -406,6 +409,8 @@ def addrRegReg : def addrDefault : ComplexPattern; +def addrimm10 : ComplexPattern; + //===----------------------------------------------------------------------===// // Instructions specific format //===----------------------------------------------------------------------===// diff --git a/lib/Target/Mips/MipsMSAInstrInfo.td b/lib/Target/Mips/MipsMSAInstrInfo.td index b23cfe60056..b6c6093fd2f 100644 --- a/lib/Target/Mips/MipsMSAInstrInfo.td +++ b/lib/Target/Mips/MipsMSAInstrInfo.td @@ -94,8 +94,6 @@ def uimm8 : Operand { def simm5 : Operand; -def simm10 : Operand; - def vsplat_uimm1 : Operand { let PrintMethod = "printUnsignedImm8"; } @@ -2292,7 +2290,7 @@ class INSVE_D_DESC : MSA_INSVE_DESC_BASE<"insve.d", int_mips_insve_d, class LD_DESC_BASE { dag OutOperandList = (outs ROWD:$wd); dag InOperandList = (ins MemOpnd:$addr); @@ -2622,7 +2620,7 @@ class SRLRI_D_DESC : MSA_BIT_D_X_DESC_BASE<"srlri.d", int_mips_srlri_d, class ST_DESC_BASE { dag OutOperandList = (outs); dag InOperandList = (ins ROWD:$wd, MemOpnd:$addr); @@ -3494,39 +3492,16 @@ class MSAPat pred = [HasMSA]> : def : MSAPat<(extractelt (v4i32 MSA128W:$ws), immZExt4:$idx), (COPY_S_W MSA128W:$ws, immZExt4:$idx)>; -def : MSAPat<(v16i8 (load addr:$addr)), (LD_B addr:$addr)>; -def : MSAPat<(v8i16 (load addr:$addr)), (LD_H addr:$addr)>; -def : MSAPat<(v4i32 (load addr:$addr)), (LD_W addr:$addr)>; -def : MSAPat<(v2i64 (load addr:$addr)), (LD_D addr:$addr)>; -def : MSAPat<(v8f16 (load addr:$addr)), (LD_H addr:$addr)>; -def : MSAPat<(v4f32 (load addr:$addr)), (LD_W addr:$addr)>; -def : MSAPat<(v2f64 (load addr:$addr)), (LD_D addr:$addr)>; +def : MSAPat<(v8f16 (load addrimm10:$addr)), (LD_H addrimm10:$addr)>; +def : MSAPat<(v4f32 (load addrimm10:$addr)), (LD_W addrimm10:$addr)>; +def : MSAPat<(v2f64 (load addrimm10:$addr)), (LD_D addrimm10:$addr)>; -def : MSAPat<(v8f16 (load addrRegImm:$addr)), (LD_H addrRegImm:$addr)>; -def : MSAPat<(v4f32 (load addrRegImm:$addr)), (LD_W addrRegImm:$addr)>; -def : MSAPat<(v2f64 (load addrRegImm:$addr)), (LD_D addrRegImm:$addr)>; - -def : MSAPat<(store (v16i8 MSA128B:$ws), addr:$addr), - (ST_B MSA128B:$ws, addr:$addr)>; -def : MSAPat<(store (v8i16 MSA128H:$ws), addr:$addr), - (ST_H MSA128H:$ws, addr:$addr)>; -def : MSAPat<(store (v4i32 MSA128W:$ws), addr:$addr), - (ST_W MSA128W:$ws, addr:$addr)>; -def : MSAPat<(store (v2i64 MSA128D:$ws), addr:$addr), - (ST_D MSA128D:$ws, addr:$addr)>; -def : MSAPat<(store (v8f16 MSA128H:$ws), addr:$addr), - (ST_H MSA128H:$ws, addr:$addr)>; -def : MSAPat<(store (v4f32 MSA128W:$ws), addr:$addr), - (ST_W MSA128W:$ws, addr:$addr)>; -def : MSAPat<(store (v2f64 MSA128D:$ws), addr:$addr), - (ST_D MSA128D:$ws, addr:$addr)>; - -def ST_FH : MSAPat<(store (v8f16 MSA128H:$ws), addrRegImm:$addr), - (ST_H MSA128H:$ws, addrRegImm:$addr)>; -def ST_FW : MSAPat<(store (v4f32 MSA128W:$ws), addrRegImm:$addr), - (ST_W MSA128W:$ws, addrRegImm:$addr)>; -def ST_FD : MSAPat<(store (v2f64 MSA128D:$ws), addrRegImm:$addr), - (ST_D MSA128D:$ws, addrRegImm:$addr)>; +def ST_FH : MSAPat<(store (v8f16 MSA128H:$ws), addrimm10:$addr), + (ST_H MSA128H:$ws, addrimm10:$addr)>; +def ST_FW : MSAPat<(store (v4f32 MSA128W:$ws), addrimm10:$addr), + (ST_W MSA128W:$ws, addrimm10:$addr)>; +def ST_FD : MSAPat<(store (v2f64 MSA128D:$ws), addrimm10:$addr), + (ST_D MSA128D:$ws, addrimm10:$addr)>; class MSA_FABS_PSEUDO_DESC_BASE(Addr)) { + EVT ValTy = Addr.getValueType(); + Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy); Offset = CurDAG->getTargetConstant(0, ValTy); return true; } + return false; +} + +/// Match frameindex+offset and frameindex|offset +bool MipsSEDAGToDAGISel::selectAddrFrameIndexOffset(SDValue Addr, SDValue &Base, + SDValue &Offset, + unsigned OffsetBits) const { + if (CurDAG->isBaseWithConstantOffset(Addr)) { + ConstantSDNode *CN = dyn_cast(Addr.getOperand(1)); + if (isIntN(OffsetBits, CN->getSExtValue())) { + EVT ValTy = Addr.getValueType(); + + // If the first operand is a FI, get the TargetFI Node + if (FrameIndexSDNode *FIN = dyn_cast + (Addr.getOperand(0))) + Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy); + else + Base = Addr.getOperand(0); + + Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy); + return true; + } + } + return false; +} + +/// ComplexPattern used on MipsInstrInfo +/// Used on Mips Load/Store instructions +bool MipsSEDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base, + SDValue &Offset) const { + // if Address is FI, get the TargetFrameIndex. + if (selectAddrFrameIndex(Addr, Base, Offset)) + return true; // on PIC code Load GA if (Addr.getOpcode() == MipsISD::Wrapper) { @@ -275,21 +306,8 @@ bool MipsSEDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base, } // Addresses of the form FI+const or FI|const - if (CurDAG->isBaseWithConstantOffset(Addr)) { - ConstantSDNode *CN = dyn_cast(Addr.getOperand(1)); - if (isInt<16>(CN->getSExtValue())) { - - // If the first operand is a FI, get the TargetFI Node - if (FrameIndexSDNode *FIN = dyn_cast - (Addr.getOperand(0))) - Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy); - else - Base = Addr.getOperand(0); - - Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy); - return true; - } - } + if (selectAddrFrameIndexOffset(Addr, Base, Offset, 16)) + return true; // Operand is a result from an ADD. if (Addr.getOpcode() == ISD::ADD) { @@ -343,27 +361,25 @@ bool MipsSEDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base, selectAddrDefault(Addr, Base, Offset); } +bool MipsSEDAGToDAGISel::selectAddrRegImm10(SDValue Addr, SDValue &Base, + SDValue &Offset) const { + if (selectAddrFrameIndex(Addr, Base, Offset)) + return true; + + if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10)) + return true; + + return false; +} + /// Used on microMIPS Load/Store unaligned instructions (12-bit offset) bool MipsSEDAGToDAGISel::selectAddrRegImm12(SDValue Addr, SDValue &Base, SDValue &Offset) const { - EVT ValTy = Addr.getValueType(); + if (selectAddrFrameIndex(Addr, Base, Offset)) + return true; - // Addresses of the form FI+const or FI|const - if (CurDAG->isBaseWithConstantOffset(Addr)) { - ConstantSDNode *CN = dyn_cast(Addr.getOperand(1)); - if (isInt<12>(CN->getSExtValue())) { - - // If the first operand is a FI then get the TargetFI Node - if (FrameIndexSDNode *FIN = dyn_cast - (Addr.getOperand(0))) - Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy); - else - Base = Addr.getOperand(0); - - Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy); - return true; - } - } + if (selectAddrFrameIndexOffset(Addr, Base, Offset, 12)) + return true; return false; } @@ -374,6 +390,17 @@ bool MipsSEDAGToDAGISel::selectIntAddrMM(SDValue Addr, SDValue &Base, selectAddrDefault(Addr, Base, Offset); } +bool MipsSEDAGToDAGISel::selectIntAddrMSA(SDValue Addr, SDValue &Base, + SDValue &Offset) const { + if (selectAddrRegImm10(Addr, Base, Offset)) + return true; + + if (selectAddrDefault(Addr, Base, Offset)) + return true; + + return false; +} + // Select constant vector splats. // // Returns true and sets Imm if: diff --git a/lib/Target/Mips/MipsSEISelDAGToDAG.h b/lib/Target/Mips/MipsSEISelDAGToDAG.h index dc52064c983..ba84a6d397e 100644 --- a/lib/Target/Mips/MipsSEISelDAGToDAG.h +++ b/lib/Target/Mips/MipsSEISelDAGToDAG.h @@ -40,6 +40,10 @@ private: SDNode *selectAddESubE(unsigned MOp, SDValue InFlag, SDValue CmpLHS, SDLoc DL, SDNode *Node) const; + bool selectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset) const; + bool selectAddrFrameIndexOffset(SDValue Addr, SDValue &Base, SDValue &Offset, + unsigned OffsetBits) const; + virtual bool selectAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset) const; @@ -52,12 +56,18 @@ private: virtual bool selectIntAddr(SDValue Addr, SDValue &Base, SDValue &Offset) const; + virtual bool selectAddrRegImm10(SDValue Addr, SDValue &Base, + SDValue &Offset) const; + virtual bool selectAddrRegImm12(SDValue Addr, SDValue &Base, SDValue &Offset) const; virtual bool selectIntAddrMM(SDValue Addr, SDValue &Base, SDValue &Offset) const; + virtual bool selectIntAddrMSA(SDValue Addr, SDValue &Base, + SDValue &Offset) const; + /// \brief Select constant vector splats. virtual bool selectVSplat(SDNode *N, APInt &Imm) const; /// \brief Select constant vector splats whose value fits in a given integer. diff --git a/test/CodeGen/Mips/msa/arithmetic_float.ll b/test/CodeGen/Mips/msa/arithmetic_float.ll index dc387212920..86e57ac85a3 100644 --- a/test/CodeGen/Mips/msa/arithmetic_float.ll +++ b/test/CodeGen/Mips/msa/arithmetic_float.ll @@ -295,7 +295,8 @@ define void @fexp2_v2f64_2(<2 x double>* %c, <2 x double>* %a) nounwind { ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) %2 = tail call <2 x double> @llvm.exp2.v2f64 (<2 x double> %1) %3 = fmul <2 x double> , %2 - ; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], %lo( + ; CHECK-DAG: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0([[G_PTR]]) ; CHECK-DAG: fexp2.d [[R4:\$w[0-9]+]], [[R3]], [[R1]] store <2 x double> %3, <2 x double>* %c ; CHECK-DAG: st.d [[R4]], 0($4) diff --git a/test/CodeGen/Mips/msa/basic_operations.ll b/test/CodeGen/Mips/msa/basic_operations.ll index 0169a0780d3..2725e9aac85 100644 --- a/test/CodeGen/Mips/msa/basic_operations.ll +++ b/test/CodeGen/Mips/msa/basic_operations.ll @@ -18,10 +18,12 @@ define void @const_v16i8() nounwind { ; MIPS32-AE: ldi.b [[R1:\$w[0-9]+]], 1 store volatile <16 x i8> , <16 x i8>*@v16i8 - ; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], %lo( + ; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0([[G_PTR]]) store volatile <16 x i8> , <16 x i8>*@v16i8 - ; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], %lo( + ; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0([[G_PTR]]) store volatile <16 x i8> , <16 x i8>*@v16i8 ; MIPS32-BE: ldi.h [[R1:\$w[0-9]+]], 256 @@ -35,7 +37,8 @@ define void @const_v16i8() nounwind { ; MIPS32-AE-DAG: fill.w [[R1:\$w[0-9]+]], [[R2]] store volatile <16 x i8> , <16 x i8>*@v16i8 - ; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], %lo( + ; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0([[G_PTR]]) ret void ; MIPS32-AE: .size const_v16i8 @@ -51,7 +54,8 @@ define void @const_v8i16() nounwind { ; MIPS32-AE: ldi.h [[R1:\$w[0-9]+]], 1 store volatile <8 x i16> , <8 x i16>*@v8i16 - ; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], %lo( + ; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[G_PTR]]) store volatile <8 x i16> , <8 x i16>*@v8i16 ; MIPS32-AE: ldi.b [[R1:\$w[0-9]+]], 4 @@ -64,7 +68,8 @@ define void @const_v8i16() nounwind { ; MIPS32-AE-DAG: fill.w [[R1:\$w[0-9]+]], [[R2]] store volatile <8 x i16> , <8 x i16>*@v8i16 - ; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], %lo( + ; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[G_PTR]]) ret void ; MIPS32-AE: .size const_v8i16 @@ -80,7 +85,8 @@ define void @const_v4i32() nounwind { ; MIPS32-AE: ldi.w [[R1:\$w[0-9]+]], 1 store volatile <4 x i32> , <4 x i32>*@v4i32 - ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], %lo( + ; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) store volatile <4 x i32> , <4 x i32>*@v4i32 ; MIPS32-AE: ldi.b [[R1:\$w[0-9]+]], 1 @@ -89,10 +95,12 @@ define void @const_v4i32() nounwind { ; MIPS32-AE: ldi.h [[R1:\$w[0-9]+]], 1 store volatile <4 x i32> , <4 x i32>*@v4i32 - ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], %lo( + ; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) store volatile <4 x i32> , <4 x i32>*@v4i32 - ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], %lo( + ; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) ret void ; MIPS32-AE: .size const_v4i32 @@ -117,10 +125,12 @@ define void @const_v2i64() nounwind { ; MIPS32-AE: ldi.d [[R1:\$w[0-9]+]], 1 store volatile <2 x i64> , <2 x i64>*@v2i64 - ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], %lo( + ; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) store volatile <2 x i64> , <2 x i64>*@v2i64 - ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], %lo( + ; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) ret void ; MIPS32-AE: .size const_v2i64 diff --git a/test/CodeGen/Mips/msa/basic_operations_float.ll b/test/CodeGen/Mips/msa/basic_operations_float.ll index 1f538108a1f..a405e1b6de5 100644 --- a/test/CodeGen/Mips/msa/basic_operations_float.ll +++ b/test/CodeGen/Mips/msa/basic_operations_float.ll @@ -17,7 +17,8 @@ define void @const_v4f32() nounwind { ; MIPS32: fill.w [[R2:\$w[0-9]+]], [[R1]] store volatile <4 x float> , <4 x float>*@v4f32 - ; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo( + ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; MIPS32: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) store volatile <4 x float> , <4 x float>*@v4f32 ; MIPS32: lui [[R1:\$[0-9]+]], 18304 @@ -25,10 +26,12 @@ define void @const_v4f32() nounwind { ; MIPS32: fill.w [[R3:\$w[0-9]+]], [[R2]] store volatile <4 x float> , <4 x float>*@v4f32 - ; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo( + ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; MIPS32: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) store volatile <4 x float> , <4 x float>*@v4f32 - ; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo( + ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; MIPS32: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) ret void ; MIPS32: .size const_v4f32 @@ -41,22 +44,28 @@ define void @const_v2f64() nounwind { ; MIPS32: ldi.b [[R1:\$w[0-9]+]], 0 store volatile <2 x double> , <2 x double>*@v2f64 - ; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo( + ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; MIPS32: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) store volatile <2 x double> , <2 x double>*@v2f64 - ; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo( + ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; MIPS32: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) store volatile <2 x double> , <2 x double>*@v2f64 - ; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo( + ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; MIPS32: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) store volatile <2 x double> , <2 x double>*@v2f64 - ; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo( + ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; MIPS32: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) store volatile <2 x double> , <2 x double>*@v2f64 - ; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo( + ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; MIPS32: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) store volatile <2 x double> , <2 x double>*@v2f64 - ; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo( + ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; MIPS32: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) ret void ; MIPS32: .size const_v2f64 diff --git a/test/CodeGen/Mips/msa/shift-dagcombine.ll b/test/CodeGen/Mips/msa/shift-dagcombine.ll index 0d809fb4fbf..322acff3ff4 100644 --- a/test/CodeGen/Mips/msa/shift-dagcombine.ll +++ b/test/CodeGen/Mips/msa/shift-dagcombine.ll @@ -37,7 +37,8 @@ define void @lshr_v4i32(<4 x i32>* %c) nounwind { %2 = lshr <4 x i32> , ; CHECK-NOT: srl - ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], %lo + ; CHECK-DAG: addiu [[CPOOL:\$[0-9]+]], {{.*}}, %lo($ + ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0([[CPOOL]]) ; CHECK-NOT: srl store volatile <4 x i32> %2, <4 x i32>* %c ; CHECK-DAG: st.w [[R1]], 0($4) diff --git a/test/CodeGen/Mips/msa/shuffle.ll b/test/CodeGen/Mips/msa/shuffle.ll index 316c669c3ac..81aefbcace1 100644 --- a/test/CodeGen/Mips/msa/shuffle.ll +++ b/test/CodeGen/Mips/msa/shuffle.ll @@ -7,7 +7,8 @@ define void @vshf_v16i8_0(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind %1 = load <16 x i8>* %a ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5) %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <16 x i32> - ; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], %lo + ; CHECK-DAG: addiu [[PTR_A:\$[0-9]+]], {{.*}}, %lo($ + ; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0([[PTR_A]]) ; CHECK-DAG: vshf.b [[R3]], [[R1]], [[R1]] store <16 x i8> %2, <16 x i8>* %c ; CHECK-DAG: st.b [[R3]], 0($4) @@ -37,7 +38,8 @@ define void @vshf_v16i8_2(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind %2 = load <16 x i8>* %b ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6) %3 = shufflevector <16 x i8> %1, <16 x i8> %2, <16 x i32> - ; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], %lo + ; CHECK-DAG: addiu [[PTR_A:\$[0-9]+]], {{.*}}, %lo($ + ; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0([[PTR_A]]) ; CHECK-DAG: vshf.b [[R3]], [[R2]], [[R2]] store <16 x i8> %3, <16 x i8>* %c ; CHECK-DAG: st.b [[R3]], 0($4) @@ -54,7 +56,8 @@ define void @vshf_v16i8_3(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind %2 = load <16 x i8>* %b ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6) %3 = shufflevector <16 x i8> %1, <16 x i8> %2, <16 x i32> - ; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], %lo + ; CHECK-DAG: addiu [[PTR_A:\$[0-9]+]], {{.*}}, %lo($ + ; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0([[PTR_A]]) ; CHECK-DAG: vshf.b [[R3]], [[R1]], [[R2]] store <16 x i8> %3, <16 x i8>* %c ; CHECK-DAG: st.b [[R3]], 0($4) @@ -83,7 +86,8 @@ define void @vshf_v8i16_0(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind %1 = load <8 x i16>* %a ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5) %2 = shufflevector <8 x i16> %1, <8 x i16> undef, <8 x i32> - ; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], %lo + ; CHECK-DAG: addiu [[PTR_A:\$[0-9]+]], {{.*}}, %lo($ + ; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], 0([[PTR_A]]) ; CHECK-DAG: vshf.h [[R3]], [[R1]], [[R1]] store <8 x i16> %2, <8 x i16>* %c ; CHECK-DAG: st.h [[R3]], 0($4) @@ -113,7 +117,8 @@ define void @vshf_v8i16_2(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind %2 = load <8 x i16>* %b ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6) %3 = shufflevector <8 x i16> %1, <8 x i16> %2, <8 x i32> - ; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], %lo + ; CHECK-DAG: addiu [[PTR_A:\$[0-9]+]], {{.*}}, %lo($ + ; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], 0([[PTR_A]]) ; CHECK-DAG: vshf.h [[R3]], [[R2]], [[R2]] store <8 x i16> %3, <8 x i16>* %c ; CHECK-DAG: st.h [[R3]], 0($4) @@ -130,7 +135,8 @@ define void @vshf_v8i16_3(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind %2 = load <8 x i16>* %b ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6) %3 = shufflevector <8 x i16> %1, <8 x i16> %2, <8 x i32> - ; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], %lo + ; CHECK-DAG: addiu [[PTR_A:\$[0-9]+]], {{.*}}, %lo($ + ; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], 0([[PTR_A]]) ; CHECK-DAG: vshf.h [[R3]], [[R1]], [[R2]] store <8 x i16> %3, <8 x i16>* %c ; CHECK-DAG: st.h [[R3]], 0($4) @@ -207,7 +213,8 @@ define void @vshf_v4i32_3(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind %2 = load <4 x i32>* %b ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) %3 = shufflevector <4 x i32> %1, <4 x i32> %2, <4 x i32> - ; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], %lo + ; CHECK-DAG: addiu [[PTR_A:\$[0-9]+]], {{.*}}, %lo($ + ; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0([[PTR_A]]) ; CHECK-DAG: vshf.w [[R3]], [[R1]], [[R2]] store <4 x i32> %3, <4 x i32>* %c ; CHECK-DAG: st.w [[R3]], 0($4) @@ -236,7 +243,8 @@ define void @vshf_v2i64_0(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind %1 = load <2 x i64>* %a ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) %2 = shufflevector <2 x i64> %1, <2 x i64> undef, <2 x i32> - ; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], %lo + ; CHECK-DAG: addiu [[PTR_A:\$[0-9]+]], {{.*}}, %lo($ + ; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0([[PTR_A]]) ; CHECK-DAG: vshf.d [[R3]], [[R1]], [[R1]] store <2 x i64> %2, <2 x i64>* %c ; CHECK-DAG: st.d [[R3]], 0($4) @@ -266,7 +274,8 @@ define void @vshf_v2i64_2(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind %2 = load <2 x i64>* %b ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) %3 = shufflevector <2 x i64> %1, <2 x i64> %2, <2 x i32> - ; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], %lo + ; CHECK-DAG: addiu [[PTR_A:\$[0-9]+]], {{.*}}, %lo($ + ; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0([[PTR_A]]) ; CHECK-DAG: vshf.d [[R3]], [[R2]], [[R2]] store <2 x i64> %3, <2 x i64>* %c ; CHECK-DAG: st.d [[R3]], 0($4) @@ -283,7 +292,8 @@ define void @vshf_v2i64_3(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind %2 = load <2 x i64>* %b ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) %3 = shufflevector <2 x i64> %1, <2 x i64> %2, <2 x i32> - ; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], %lo + ; CHECK-DAG: addiu [[PTR_A:\$[0-9]+]], {{.*}}, %lo($ + ; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0([[PTR_A]]) ; CHECK-DAG: vshf.d [[R3]], [[R1]], [[R2]] store <2 x i64> %3, <2 x i64>* %c ; CHECK-DAG: st.d [[R3]], 0($4)