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Simplify iterator usage now that we have next(). Also don't pass iterators by reference now that MachineInstr* are in an ilist

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11732 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Alkis Evlogimenos 2004-02-23 04:12:30 +00:00
parent a118ae1c9d
commit fc2b449a17
1 changed files with 7 additions and 11 deletions
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18
lib/CodeGen/RegAllocSimple.cpp
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@ -24,6 +24,7 @@
#include "llvm/Target/TargetMachine.h"
#include "Support/Debug.h"
#include "Support/Statistic.h"
#include "Support/STLExtras.h"
#include <iostream>
using namespace llvm;
@ -78,10 +79,10 @@ namespace {
/// Moves value from memory into that register
unsigned reloadVirtReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &I, unsigned VirtReg);
MachineBasicBlock::iterator I, unsigned VirtReg);
/// Saves reg value on the stack (maps virtual register to stack value)
void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I,
void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned VirtReg, unsigned PhysReg);
};
@ -123,7 +124,7 @@ unsigned RegAllocSimple::getFreeReg(unsigned virtualReg) {
}
unsigned RegAllocSimple::reloadVirtReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &I,
MachineBasicBlock::iterator I,
unsigned VirtReg) {
const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(VirtReg);
int FrameIdx = getStackSpaceFor(VirtReg, RC);
@ -136,7 +137,7 @@ unsigned RegAllocSimple::reloadVirtReg(MachineBasicBlock &MBB,
}
void RegAllocSimple::spillVirtReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &I,
MachineBasicBlock::iterator I,
unsigned VirtReg, unsigned PhysReg) {
const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(VirtReg);
int FrameIdx = getStackSpaceFor(VirtReg, RC);
@ -193,17 +194,12 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
"Two address instruction invalid!");
physReg = MI->getOperand(1).getReg();
++MI;
spillVirtReg(MBB, MI, virtualReg, physReg);
--MI;
spillVirtReg(MBB, next(MI), virtualReg, physReg);
MI->getOperand(1).setDef();
MI->RemoveOperand(0);
break; // This is the last operand to process
}
++MI;
spillVirtReg(MBB, MI, virtualReg, physReg);
--MI;
spillVirtReg(MBB, next(MI), virtualReg, physReg);
} else {
physReg = reloadVirtReg(MBB, MI, virtualReg);
Virt2PhysRegMap[virtualReg] = physReg;