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[mips][mips64r6] Add aui, daui, dahi, and dati

Browse Source 
Summary: Depends on D3671

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3759

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208857 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders 2014-05-15 10:27:19 +00:00
parent ca323cf916
commit fc4953bff2
5 changed files with 64 additions and 5 deletions
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40
lib/Target/Mips/Mips32r6InstrFormats.td
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@ -23,9 +23,18 @@ class MipsR6Inst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>,
//
//===----------------------------------------------------------------------===//
def OPGROUP_COP1 { bits<6> Value = 0b010001; }
def OPGROUP_COP1 { bits<6> Value = 0b010001; }
def OPGROUP_AUI { bits<6> Value = 0b001111; }
def OPGROUP_DAUI { bits<6> Value = 0b011101; }
def OPGROUP_REGIMM { bits<6> Value = 0b000001; }
def OPGROUP_SPECIAL { bits<6> Value = 0b000000; }
class OPCODE5<bits<5> Val> {
bits<5> Value = Val;
}
def OPCODE5_DAHI : OPCODE5<0b00110>;
def OPCODE5_DATI : OPCODE5<0b11110>;
class FIELD_FMT<bits<5> Val> {
bits<5> Value = Val;
}
@ -38,6 +47,23 @@ def FIELD_FMT_D : FIELD_FMT<0b10001>;
//
//===----------------------------------------------------------------------===//
class AUI_FM : MipsR6Inst {
bits<5> rs;
bits<5> rt;
bits<16> imm;
bits<32> Inst;
let Inst{31-26} = OPGROUP_AUI.Value;
let Inst{25-21} = rs;
let Inst{20-16} = rt;
let Inst{15-0} = imm;
}
class DAUI_FM : AUI_FM {
let Inst{31-26} = OPGROUP_DAUI.Value;
}
class COP1_3R_FM<bits<6> funct, FIELD_FMT Format> : MipsR6Inst {
bits<5> ft;
bits<5> fs;
@ -67,3 +93,15 @@ class SPECIAL_3R_FM<bits<5> mulop, bits<6> funct> : MipsR6Inst {
let Inst{10-6} = mulop;
let Inst{5-0} = funct;
}
class REGIMM_FM<OPCODE5 Operation> : MipsR6Inst {
bits<5> rs;
bits<16> imm;
bits<32> Inst;
let Inst{31-26} = OPGROUP_REGIMM.Value;
let Inst{25-21} = rs;
let Inst{20-16} = Operation.Value;
let Inst{15-0} = imm;
}

12
lib/Target/Mips/Mips32r6InstrInfo.td
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@ -58,6 +58,7 @@ include "Mips32r6InstrFormats.td"
//
//===----------------------------------------------------------------------===//
class AUI_ENC : AUI_FM;
class DIV_ENC : SPECIAL_3R_FM<0b00010, 0b011010>;
class DIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011011>;
class MOD_ENC : SPECIAL_3R_FM<0b00011, 0b011010>;
@ -75,6 +76,15 @@ class SEL_S_ENC : COP1_3R_FM<0b010000, FIELD_FMT_S>;
//
//===----------------------------------------------------------------------===//
class AUI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
dag OutOperandList = (outs GPROpnd:$rs);
dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm");
list<dag> Pattern = [];
}
class AUI_DESC : AUI_DESC_BASE<"aui", GPR32Opnd>;
class DIVMOD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
dag OutOperandList = (outs GPROpnd:$rd);
dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
@ -119,7 +129,7 @@ class SEL_S_DESC : SEL_DESC_BASE<"sel.s", FGR32Opnd>;
def ADDIUPC;
def ALIGN; // Known as as BALIGN in DSP ASE
def ALUIPC;
def AUI;
def AUI : AUI_ENC, AUI_DESC, ISA_MIPS32R6;
def AUIPC;
def BALC;
def BC1EQZ;

12
lib/Target/Mips/Mips64r6InstrInfo.td
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@ -25,6 +25,9 @@
//
//===----------------------------------------------------------------------===//
class DAUI_ENC : DAUI_FM;
class DAHI_ENC : REGIMM_FM<OPCODE5_DAHI>;
class DATI_ENC : REGIMM_FM<OPCODE5_DATI>;
class DDIV_ENC : SPECIAL_3R_FM<0b00010, 0b011110>;
class DDIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011111>;
class DMOD_ENC : SPECIAL_3R_FM<0b00011, 0b011110>;
@ -40,6 +43,9 @@ class DMULU_ENC : SPECIAL_3R_FM<0b00010, 0b111001>;
//
//===----------------------------------------------------------------------===//
class DAHI_DESC : AUI_DESC_BASE<"dahi", GPR64Opnd>;
class DATI_DESC : AUI_DESC_BASE<"dati", GPR64Opnd>;
class DAUI_DESC : AUI_DESC_BASE<"daui", GPR64Opnd>;
class DDIV_DESC : DIVMOD_DESC_BASE<"ddiv", GPR64Opnd>;
class DDIVU_DESC : DIVMOD_DESC_BASE<"ddivu", GPR64Opnd>;
class DMOD_DESC : DIVMOD_DESC_BASE<"dmod", GPR64Opnd>;
@ -55,10 +61,10 @@ class DMULU_DESC : MUL_R6_DESC_BASE<"dmulu", GPR64Opnd>;
//
//===----------------------------------------------------------------------===//
def DAHI;
def DAHI : DAHI_ENC, DAHI_DESC, ISA_MIPS64R6;
def DALIGN;
def DATI;
def DAUI;
def DATI : DATI_ENC, DATI_DESC, ISA_MIPS64R6;
def DAUI : DAUI_ENC, DAUI_DESC, ISA_MIPS64R6;
def DBITSWAP;
def DDIV : DDIV_ENC, DDIV_DESC, ISA_MIPS64R6;
def DDIVU : DDIVU_ENC, DDIVU_DESC, ISA_MIPS64R6;

1
test/MC/Mips/mips32r6/valid.s
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@ -4,6 +4,7 @@
.set noat
# FIXME: Add the instructions carried forward from older ISA's
aui $3,$2,-23 # CHECK: aui $3, $2, -23 # encoding: [0x3c,0x62,0xff,0xe9]
div $2,$3,$4 # CHECK: div $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9a]
divu $2,$3,$4 # CHECK: divu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9b]
mod $2,$3,$4 # CHECK: mod $2, $3, $4 # encoding: [0x00,0x64,0x10,0xda]

4
test/MC/Mips/mips64r6/valid.s
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@ -4,6 +4,10 @@
.set noat
# FIXME: Add the instructions carried forward from older ISA's
aui $3,$2,-23 # CHECK: aui $3, $2, -23 # encoding: [0x3c,0x62,0xff,0xe9]
daui $3,$2,0x1234 # CHECK: daui $3, $2, 4660 # encoding: [0x74,0x62,0x12,0x34]
dahi $3,$3,0x5678 # CHECK: dahi $3, $3, 22136 # encoding: [0x04,0x66,0x56,0x78]
dati $3,$3,0xabcd # CHECK: dati $3, $3, 43981 # encoding: [0x04,0x7e,0xab,0xcd]
div $2,$3,$4 # CHECK: div $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9a]
divu $2,$3,$4 # CHECK: divu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9b]
mod $2,$3,$4 # CHECK: mod $2, $3, $4 # encoding: [0x00,0x64,0x10,0xda]