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Neuter the optimization I implemented with r107852 and r108258 which turn some
floating point equality comparisons into integer ones with -ffast-math. The issue is the optimization causes +0.0 != -0.0. Now the optimization is only done when one side is known to be 0.0. The other side's sign bit is masked off for the comparison. rdar://10964603 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151861 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2978,12 +2978,11 @@ ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
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SDValue Dest = Op.getOperand(4);
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DebugLoc dl = Op.getDebugLoc();
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bool SeenZero = false;
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if (canChangeToInt(LHS, SeenZero, Subtarget) &&
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canChangeToInt(RHS, SeenZero, Subtarget) &&
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// If one of the operand is zero, it's safe to ignore the NaN case since
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// we only care about equality comparisons.
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(SeenZero || (DAG.isKnownNeverNaN(LHS) && DAG.isKnownNeverNaN(RHS)))) {
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bool LHSSeenZero = false;
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bool LHSOk = canChangeToInt(LHS, LHSSeenZero, Subtarget);
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bool RHSSeenZero = false;
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bool RHSOk = canChangeToInt(RHS, RHSSeenZero, Subtarget);
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if (LHSOk && RHSOk && (LHSSeenZero || RHSSeenZero)) {
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// If unsafe fp math optimization is enabled and there are no other uses of
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// the CMP operands, and the condition code is EQ or NE, we can optimize it
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// to an integer comparison.
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@ -2992,10 +2991,13 @@ ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
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else if (CC == ISD::SETUNE)
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CC = ISD::SETNE;
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SDValue Mask = DAG.getConstant(0x7fffffff, MVT::i32);
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SDValue ARMcc;
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if (LHS.getValueType() == MVT::f32) {
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LHS = bitcastf32Toi32(LHS, DAG);
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RHS = bitcastf32Toi32(RHS, DAG);
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LHS = DAG.getNode(ISD::AND, dl, MVT::i32,
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bitcastf32Toi32(LHS, DAG), Mask);
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RHS = DAG.getNode(ISD::AND, dl, MVT::i32,
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bitcastf32Toi32(RHS, DAG), Mask);
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SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
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SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
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return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
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@ -3006,6 +3008,8 @@ ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
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SDValue RHS1, RHS2;
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expandf64Toi32(LHS, DAG, LHS1, LHS2);
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expandf64Toi32(RHS, DAG, RHS1, RHS2);
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LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask);
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RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask);
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ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
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ARMcc = DAG.getConstant(CondCode, MVT::i32);
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SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
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@ -1,24 +1,16 @@
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; RUN: llc < %s -march=arm -mcpu=cortex-a8 -mattr=+vfp2 -enable-unsafe-fp-math -enable-no-nans-fp-math | FileCheck -check-prefix=FINITE %s
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; RUN: llc < %s -march=arm -mcpu=cortex-a8 -mattr=+vfp2 -enable-unsafe-fp-math | FileCheck -check-prefix=NAN %s
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; RUN: llc < %s -march=arm -mcpu=cortex-a8 -mattr=+vfp2 -enable-unsafe-fp-math | FileCheck %s
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; rdar://7461510
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; rdar://10964603
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; Disable this optimization unless we know one of them is zero.
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define arm_apcscc i32 @t1(float* %a, float* %b) nounwind {
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entry:
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; FINITE: t1:
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; FINITE-NOT: vldr
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; FINITE: ldr
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; FINITE: ldr
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; FINITE: cmp r0, r1
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; FINITE-NOT: vcmpe.f32
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; FINITE-NOT: vmrs
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; FINITE: beq
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; NAN: t1:
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; NAN: vldr s0,
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; NAN: vldr s1,
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; NAN: vcmpe.f32 s1, s0
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; NAN: vmrs apsr_nzcv, fpscr
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; NAN: beq
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; CHECK: t1:
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; CHECK: vldr s0,
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; CHECK: vldr s1,
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; CHECK: vcmpe.f32 s1, s0
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; CHECK: vmrs apsr_nzcv, fpscr
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; CHECK: beq
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%0 = load float* %a
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%1 = load float* %b
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%2 = fcmp une float %0, %1
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@ -33,17 +25,21 @@ bb2:
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ret i32 %4
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}
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; If one side is zero, the other size sign bit is masked off to allow
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; +0.0 == -0.0
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define arm_apcscc i32 @t2(double* %a, double* %b) nounwind {
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entry:
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; FINITE: t2:
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; FINITE-NOT: vldr
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; FINITE: ldrd r0, r1, [r0]
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; FINITE-NOT: b LBB
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; FINITE: cmp r0, #0
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; FINITE: cmpeq r1, #0
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; FINITE-NOT: vcmpe.f32
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; FINITE-NOT: vmrs
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; FINITE: bne
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; CHECK: t2:
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; CHECK-NOT: vldr
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; CHECK: ldr [[REG1:(r[0-9]+)]], [r0]
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; CHECK: ldr [[REG2:(r[0-9]+)]], [r0, #4]
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; CHECK-NOT: b LBB
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; CHECK: cmp [[REG1]], #0
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; CHECK: bfc [[REG2]], #31, #1
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; CHECK: cmpeq [[REG2]], #0
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; CHECK-NOT: vcmpe.f32
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; CHECK-NOT: vmrs
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; CHECK: bne
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%0 = load double* %a
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%1 = fcmp oeq double %0, 0.000000e+00
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br i1 %1, label %bb1, label %bb2
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@ -59,13 +55,14 @@ bb2:
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define arm_apcscc i32 @t3(float* %a, float* %b) nounwind {
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entry:
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; FINITE: t3:
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; FINITE-NOT: vldr
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; FINITE: ldr r0, [r0]
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; FINITE: cmp r0, #0
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; FINITE-NOT: vcmpe.f32
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; FINITE-NOT: vmrs
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; FINITE: bne
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; CHECK: t3:
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; CHECK-NOT: vldr
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; CHECK: ldr [[REG3:(r[0-9]+)]], [r0]
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; CHECK: mvn [[REG4:(r[0-9]+)]], #-2147483648
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; CHECK: tst [[REG3]], [[REG4]]
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; CHECK-NOT: vcmpe.f32
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; CHECK-NOT: vmrs
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; CHECK: bne
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%0 = load float* %a
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%1 = fcmp oeq float %0, 0.000000e+00
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br i1 %1, label %bb1, label %bb2
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